数据搜索系统,热门电子元器件搜索
  Chinese  ▼
ALLDATASHEETCN.COM

X  

24LC41IP 数据表(PDF) 3 Page - Microchip Technology

部件名 24LC41IP
功能描述  1K/4K 2.5V Dual Mode, Dual Port I2C??Serial EEPROM
PDF  18 Pages
Scroll/Zoom Zoom In 100%  Zoom Out
制造商  MICROCHIP [Microchip Technology]
网页  http://www.microchip.com
标志 MICROCHIP - Microchip Technology

24LC41IP 数据表(HTML) 3 Page - Microchip Technology

  24LC41IP Datasheet HTML 1Page - Microchip Technology 24LC41IP Datasheet HTML 2Page - Microchip Technology 24LC41IP Datasheet HTML 3Page - Microchip Technology 24LC41IP Datasheet HTML 4Page - Microchip Technology 24LC41IP Datasheet HTML 5Page - Microchip Technology 24LC41IP Datasheet HTML 6Page - Microchip Technology 24LC41IP Datasheet HTML 7Page - Microchip Technology 24LC41IP Datasheet HTML 8Page - Microchip Technology 24LC41IP Datasheet HTML 9Page - Microchip Technology Next Button
Zoom Inzoom in Zoom Outzoom out
 3 / 18 page
background image
 2004 Microchip Technology Inc.
DS21140F-page 3
24LC41
TABLE 1-2:
AC CHARACTERISTICS (DDC MONITOR AND MICROCONTROLLER
ACCESS PORTS)
DDC Monitor Port (Bidirectional Mode) and Microcontroller Access Port
Parameter
Symbol
Standard Mode
Vcc = 4.5 - 5.5V
Fast Mode
Units
Remarks
Min
Max
Min
Max
Clock frequency
(DSCL and MSCL)
FCLK
100
400
kHz
Clock high time
(DSCL and MSCL)
THIGH
4000
600
ns
Clock low time
(DSCL and MSCL)
TLOW
4700
1300
ns
DSCL, DSDA, MSCL and
MSDA rise time
TR
1000
300
ns
(Note 1)
DSCL, DSDA, MSCL and
MSDA fall time
TF
300
300
ns
(Note 1)
Start condition hold time
THD:STA
4000
600
ns
After this period the first
clock pulse is generated
Start condition setup time
TSU:STA
4700
600
ns
Only relevant for repeated
Start condition
Data input hold time
THD:DAT
0—
0
ns
(Note 2)
Data input setup time
TSU:DAT
250
100
ns
Stop condition setup time
TSU:STO
4000
600
ns
Output valid from clock
TAA
3500
900
ns
(Note 2)
Bus free time
TBUF
4700
1300
ns
Time the bus must be free
before a new transmission
can start
Output fall time from VIH
min to VIL max
TOF
250
20 + .1
CB
250
ns
(Note 1), CB
≤ 100 pF
Input filter spike
suppression (DSCL, DSDA,
MSCL and MSDA pins)
TSP
—50
50
ns
(Note 3)
Write cycle time
TWR
10
10
ms
Byte or Page mode
DDC Monitor Port Transmit-Only Mode Parameters
Output valid from VCLK/
DWP
TVAA
2000
1000
ns
VCLK/DWP high time
TVHIGH
4000
600
ns
VCLK/DWP low time
TVLOW
4700
1300
ns
Mode transition time
TVHZ
500
500
ns
Transmit-only power-up
time
TVPU
0—
0
ns
Endurance
1M
1M
cycles
25°C, Vcc = 5.0V, Block
mode (Note 4)
Note 1:
Not 100% tested. CB = total capacitance of one bus line in pF.
2:
As a transmitter, the device must provide an internal minimum delay time to bridge the undefined region
(minimum 300 ns) of the falling edge of DSCL or MSCL to avoid unintended generation of Start or Stop
conditions.
3:
The combined TSP and VHYS specifications are due to new Schmitt Trigger inputs which provide improved
noise and spike suppression. This eliminates the need for a TI specification for standard operation.
4:
This parameter is not tested but ensured by characterization. For endurance estimates in a specific
application, please consult the Total Endurance™ model which can be obtained from our web site.



Html Pages

1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18


数据表 下载

Go To PDF Page


链接网址



ALLDATASHEET是否为您带来帮助?  [ DONATE ] 

关于 Alldatasheet   |   广告服务   |   联系我们   |   隐私政策   |   数据表链接    |   链接交换   |   制造商名单
All Rights Reserved©Alldatasheet.com


Mirror Sites
English : Alldatasheet.com  |   English : Alldatasheet.net  |   Chinese : Alldatasheetcn.com  |   German : Alldatasheetde.com  |   Japanese : Alldatasheet.jp
Russian : Alldatasheetru.com  |   Korean : Alldatasheet.co.kr  |   Spanish : Alldatasheet.es  |   French : Alldatasheet.fr  |   Italian : Alldatasheetit.com
Portuguese : Alldatasheetpt.com  |   Polish : Alldatasheet.pl  |   Vietnamese : Alldatasheet.vn
Indian : Alldatasheet.in  |   Mexican : Alldatasheet.com.mx  |   British : Alldatasheet.co.uk  |   New Zealand : Alldatasheet.co.nz
Family Site : ic2ic.com  |   icmetro.com