 2004 Microchip Technology Inc.

DS21140F-page 5

24LC41

2.3.1

BIDIRECTIONAL MODE

The DDC Monitor Port can be switched into the

Bidirectional mode (Figure 2-3) by applying a valid

high-to-low transition on the Bidirectional mode Clock

(DSCL). When the device has been switched into the

Bidirectional mode, the VCLK/DWP input is disre-

garded, with the exception that a logic high level is

required to enable write capability. This mode supports

a 2-wire bidirectional data transmission protocol. In this

protocol, a device that sends data on the bus is defined

to be the transmitter, and a device that receives data

from the bus is defined to be the receiver. The bus must

be controlled by a master device that generates the

Bidirectional mode Clock (DSCL), controls access to

the bus and generates the Start and Stop conditions,

while the DDC Monitor Port acts as the slave. Both

master and slave can operate as transmitter or

receiver, but the master device determines which mode

is activated.

2.4

Microcontroller Access Port

The Microcontroller Access Port supports a bidirec-

tional 2-wire bus and data transmission protocol. A

device that sends data onto the bus is defined as

transmitter, and a device receiving data as receiver.

The bus has to be controlled by a master device which

generates the serial clock (MSCL), controls the bus

access, and generates the Start and Stop conditions,

while the Microcontroller Access Port works as slave.

Both master and slave can operate as transmitter or

receiver, but the master device determines which mode

is activated.

FIGURE 2-3:

MODE TRANSITION

DSCL

DSDA

VCLK/DWP

Bidirectional Mode

Transmit-only Mode