 2004 Microchip Technology Inc.

DS21140F-page 7

24LC41

FIGURE 3-1:

DATA TRANSFER SEQUENCE ON THE SERIAL BUS

FIGURE 3-2:

BUS TIMING START/STOP

FIGURE 3-3:

BUS TIMING DATA

FIGURE 3-4:

CONTROL BYTE ALLOCATION

DSCL

DSDA

(D)

(D)

(C)

Start

Condition

Address or

Acknowledge

Valid

Data

Allowed

to Change

Stop

Condition

or

MSCL

or

MSDA

MSCL

DSDA

Start

Stop

or

MSCL

IN

or

MSDA

IN

DSCL

DSDA

DSDA

or

MSCL

IN

OR

MSDA

IN

OR

MSDA

OUT

X = Don’t care. B0 is don’t care for DDC Monitor Port, but is used by the Microcontroller Access Port to select which of the two 256

word blocks of memory are to be accessed.

R/W

A

1

0

10X

X

X

READ/WRITE

Start

SLAVE ADDRESS