Dual 8-/10-/12-/14-/16-Bit

250 MSPS Digital-to-Analog Converters

AD9741/AD9743/AD9745/AD9746/AD9747

Rev. 0

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FEATURES

High dynamic range, dual DACs

Low noise and intermodulation distortion

Single carrier WCDMA ACLR = 80 dBc @ 61.44 MHz IF

Innovative switching output stage permits useable outputs

beyond Nyquist frequency

LVCMOS inputs with dual-port or optional interleaved

single-port operation

Differential analog current outputs are programmable from

8.6 mA to 31.7 mA full scale

Auxiliary 10-bit current DACs with source/sink capability for

external offset nulling

Internal 1.2 V precision reference voltage source

Operates from 1.8 V and 3.3 V supplies

315 mW power dissipation

Small footprint, Pb-free, 72-

Lead LFCSP

APPLICATIONS

Wireless infrastructure:

WCDMA, CDMA2000, TD-SCDMA, WiMAX

Wideband communications:

LMDS/MMDS, point-to-point

Instrumentation:

RF signal generators, arbitrary waveform generators

GENERAL DESCRIPTION

The AD9741/AD9743/AD9745/AD9746/AD9747 are pin-

compatible, high dynamic range, dual digital-to-analog

converters (DACs) with 8-/10-/12-/ 14-/16-bit resolutions

and sample rates of up to 250 MSPS. The devices include

specific features for direct conversion transmit applications,

including gain and offset compensation, and they interface

seamlessly with analog quadrature modulators, such as the

ADL5370.

A proprietary, dynamic output architecture permits synthesis

of analog outputs even above Nyquist by shifting energy away

from the fundamental and into the image frequency.

Full programmability is provided through a serial peripheral

interface (SPI) port. In addition, some pin-programmable

features are offered for those applications without a controller.

PRODUCT HIGHLIGHTS

1.

Low noise and intermodulation distortion (IMD) enables

high quality synthesis of wideband signals.

2.

Proprietary switching output for enhanced dynamic

performance.

3.

Programmable current outputs and dual auxiliary DACs

provide flexibility and system enhancements.

FUNCTIONAL BLOCK DIAGRAM

16-BIT

DAC1

16-BIT

DAC2

INTERFACE LOGIC

GAIN

DAC

GAIN

DAC

OFFSET

DAC

OFFSET

DAC

INTERNAL

REFERENCE

AND

BIAS

SERIAL

PERIPHERAL

INTERFACE

10

CMOS

INTERFACE

CLKP

CLKN

PID<15:0>

P2D<15:0>

IOUT1P

IOUT1N

IOUT2P

IOUT2N

AUX1P

AUX1N

AUX2P

AUX2N

Figure 1.