AD9747-EBZ datasheet(22/28 Pages) AD

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AD9741/AD9743/AD9745/AD9746/AD9747

Rev. 0 | Page 22 of 28

DIGITAL INPUTS AND OUTPUTS

The AD9741/AD9743/AD9745/AD9746/AD9747 can operate

in two data input modes: dual-port mode and single-port mode.

For the default dual-port mode (ONEPORT = 0), each DAC

receives data from a dedicated input port. In single-port mode

(ONEPORT = 1), however, both DACs receive data from Port 1.

In single-port mode, DAC1 and DAC2 data is interleaved and

the IQSEL input is used to steer data to the correct DAC.

In single-port mode, when the IQSEL input is high, Port 1

data is delivered to DAC1 and when IQSEL is low, Port 1 data

is delivered to DAC2. The IQSEL input should always coincide

and be time-aligned with the other data bus signals. In single-

port mode, minimum setup and hold times apply to the IQSEL

input as well as to the input data signals. In dual-port mode, the

IQSEL input is ignored.

In dual-port mode, the data must be delivered at the sample rate

(up to 250 MSPS). In single-port mode, data must be delivered

at twice the sample rate. Because the data inputs function only

up to 250 MSPS, it is only practical to operate the DAC clock at

up to 125 MHz in single-port mode.

In both dual-port and single-port modes, a data clock output

(DCO) signal is available as a fixed time base with which to

stimulate data from an FPGA. This output signal always

operates at the sample rate. It may be inverted by asserting

the INVDCO bit.

INPUT DATA TIMING

With most DACs, signal-to-noise ratio (SNR) is a function of

the relationship between the position of the clock edges and the

point in time at which the input data changes. The AD9741/

AD9743/AD9745/AD9746/AD9747 are rising edge triggered

and thus exhibit greater SNR sensitivity when the data tran-

sition is close to this edge.

The specified minimum setup and hold times define a window

of time, within each data period, where the data is sampled

correctly. Generally, users should position data to arrive

relative to the DAC clock and well beyond the minimum

setup and minimum hold times. This becomes increasingly

more important at increasingly higher sample rates.

DUAL-PORT MODE TIMING

The timing diagram for the dual-port mode is shown in

Figure 27.

CLKP/CLKN

DCO

P1D<15:0>

P2D<15:0>

tDCO

tDBH

tDBS

Figure 27. Data Interface Timing, Dual-Port Mode

In Figure 27, data samples for DAC1 are labeled Ix and data

samples for DAC2 are labeled Qx. Note that the differential

DAC clock input is shown in a logical sense (CLKP/CLKN).

The data clock output is labeled DCO.

Setup and hold times are referenced to the positive transition of

the DAC clock. Data should arrive at the input pins such that

the minimum setup and hold times are met. Note that the data

clock output has a fixed time delay from the DAC clock and

may be a more convenient signal to use to confirm timing.

SINGLE-PORT MODE TIMING

The single-port mode timing diagram is shown in Figure 28.

CLKP/CLKN

DCO

P1D<15:0>

IQSEL

tDBS

tDBH

tDCO

Figure 28. Data Interface Timing, Single-Port Mode

In single-port mode, data for both DACs is received on the

Port 1 input bus. Ix and Qx data samples are interleaved and

arrive twice as fast as in dual-port mode. Accompanying the

data is the IQSEL input signal, which steers incoming data to its

respective DAC. When IQSEL is high, data is steered to DAC1

and when IQSEL is low, data is steered to DAC2. IQSEL should

coincide as well as be time-aligned with incoming data.

SPI PORT, RESET, AND PIN MODE

In general, when the AD9741/AD9743/AD9745/AD9746/

AD9747 are powered up, an active high pulse applied to the

RESET pin should follow. This insures the default state of all

control register bits. In addition, once the RESET pin goes low,

the SPI port can be activated, so CSB should be held high.

For applications without a controller, the AD9741/AD9743/

AD9745/AD9746/AD9747 also support pin mode operation,

which allows some functional options to be pin, selected with-

out the use of the SPI port. Pin mode is enabled anytime the

RESET pin is held high. In pin mode, the four SPI port pins

take on secondary functions, as shown in Table 16.

Table 16. SPI Pin Functions (Pin Mode)

Pin Name

Pin Mode Description

SCLK

ONEPORT (Register 0x02, Bit 6), bit value (1/0)

equals pin state (high/low)

SDIO

DATTYPE (Register 0x02, Bit 7), bit value (1/0)

equals pin state (high/low)

CSB

Enable Mix Mode, if CSB is high, Register 0x0A

is set to 0x05 putting both DAC1 and DAC2 into

mix mode

SDO

Enable full power-down, if SDO is high, Register

0x03 is set to 0xFF

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