AD9747-EBZ datasheet(23/28 Pages) AD

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AD9741/AD9743/AD9745/AD9746/AD9747

Rev. 0 | Page 23 of 28

In pin mode, all register bits are reset to their default values

with the exception of those that are controlled by the SPI pins.

Note also that the RESET pin should be allowed to float and

must be pulled low. Connect an external 10 kΩ resistor to

DVSS. This avoids unexpected behavior in noisy environments.

DRIVING THE DAC CLOCK INPUT

The DAC clock input requires a low jitter drive signal. It is a

PMOS differential pair powered from the CVDD18 supply.

Each pin can safely swing up to 800 mV p-p at a common-

mode voltage of about 400 mV. Though these levels are not

directly LVDS-compatible, CLKP and CLKN can be driven by

an ac-coupled, dc-offset LVDS signal, as shown in Figure 29.

LVDS_P_IN

CLKP

50Ω

0.1µF

LVDS_N_IN

CLKN

VCM = 400mV

Figure 29. LVDS DAC Clock Drive Circuit

Using a CMOS or TTL clock is also acceptable for lower sample

rates. It can be routed through an LVDS translator and then

ac-coupled as described previously, or alternatively, it can be

transformer-coupled and clamped, as shown in Figure 30.

50Ω

TTL OR CMOS

CLK INPUT

CLKP

CLKN

VCM = 400mV

BAV99ZXCT

HIGH SPEED

DUAL DIODE

0.1µF

Figure 30. TTL or CMOS DAC Clock Drive Circuit

If a sine wave signal is available, it can be transformer-coupled

directly to the DAC clock inputs, as shown in Figure 31.

50Ω

SINE WAVE

INPUT

CLKP

CLKN

VCM = 400mV

Figure 31. Sine Wave DAC Clock Drive Circuit

The 400 mV common-mode bias voltage can be derived from

the CVDD18 supply through a simple divider network, as

shown in Figure 32.

0.1µF

1nF

VCM = 400mV

CVDD18

CVSS

1kΩ

287Ω

Figure 32. DAC Clock VCM Circuit

It is important to use CVDD18 and CVSS for any clock bias

circuit as noise that is coupled onto the clock from another

power supply is multiplied by the DAC input signal and

degrades performance.

FULL-SCALE CURRENT GENERATION

The full-scale currents on DAC1 and DAC2 are functions of

the current drawn through an external resistor connected to

the FSADJ pin (Pin 54). The required value for this resistor is

10 kΩ. An internal amplifier sets the current through the

resistor to force a voltage equal to the band gap voltage of 1.2 V.

This develops a reference current in the resistor of 120 μA.

CURRENT

SCALING

1.2V BANDGAP

DAC1 GAIN

DAC2 GAIN

AD9747

DAC1

DAC2

DAC FULL SCALE

REFERENCE CURRENT

REFIO

FSADJ

0.1µF

10kΩ

Figure 33. Reference Circuitry

REFIO (Pin 55) should be bypassed to ground with a 0.1 μF

capacitor. The band gap voltage is present on this pin and can

be buffered for use in external circuitry. The typical output

impedance is near 5 kΩ. If desired, an external reference can

be connected to REFIO to overdrive the internal reference.

Internal current mirrors provide a means for adjusting the

DAC full-scale currents. The gain for DAC1 and DAC2 can be

adjusted independently by writing to the DAC1FSC<9:0> and

DAC2FSC<9:0> register bits. The default value of 0x01F9 for

the DAC gain registers gives an IFS of 20 mA, where IFS equals

⎟

⎠

⎞

⎜

⎝

⎛

⎟

⎠

⎞

⎜

⎝

⎛

FSC

DAC

IFS

10,000

1.2

The full-scale output current range is 8.6 mA to 31.7 mA for

256

512

768

1024

DAC GAIN CODE

Figure 34. IFS vs. DAC Gain Code

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