DSP56366 datasheet(39/110 Pages) FREESCALE

39 / 110 page

DSP56366 Technical Data, Rev. 3.1

Freescale Semiconductor

3-13

109

Data hold time from WR deassertion

tDH

0.25

× T

C − 2.0

≤ WS ≤ 3]

0.1

—

1.25

× T

C − 2.0

≤ WS ≤ 7]

8.4

—

2.25

× T

C − 2.0

[WS

≥ 8]

16.7

—

110

WR assertion to data active

—

0.75

× T

C − 3.7

[WS = 1]

2.5

—

0.25

× T

C − 3.7

≤ WS ≤ 3]

0.0

—

−0.25 × T

C − 3.7

[WS

≥ 4]

0.0

—

111

WR deassertion to data high impedance

—

0.25

× T

C + 0.2

≤ WS ≤ 3]

—2.3

1.25

× T

C + 0.2

≤ WS ≤ 7]

—10.6

2.25

× T

C + 0.2

[WS

≥ 8]

—18.9

112

Previous RD deassertion to data active (write)

—

1.25

× T

C − 4.0

≤ WS ≤ 3]

6.4

—

2.25

× T

C − 4.0

≤ WS ≤ 7]

14.7

—

3.25

× T

C − 4.0

[WS

≥ 8]

23.1

—

113

RD deassertion time

0.75

× T

C − 4.0

≤ WS ≤ 3]

2.2

—

1.75

× T

C − 4.0

≤ WS ≤ 7]

10.6

—

2.75

× T

C − 4.0

[WS

≥ 8]

18.9

—

Table 3-8 SRAM Read and Write Accesses1 (continued)

No.

Characteristics

Symbol

Expression2

Min

Max

Unit

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