DSP56366 datasheet(2/110 Pages) FREESCALE

2 / 110 page

Overview

DSP56366 Technical Data, Rev. 3.1

1-2

Freescale Semiconductor

Figure 1-1 DSP56366 Block Diagram

Data Sheet Conventions

This data sheet uses the following conventions:

OVERBAR

Used to indicate a signal that is active when pulled low (For example, the RESET pin is active

when low.)

“asserted”

Means that a high true (active high) signal is high or that a low true (active low) signal is low

“deasserted”

Means that a high true (active high) signal is low or that a low true (active low) signal is high

Examples:

Signal/Symbol

Logic State

Signal State

Voltage*

True

Asserted

VIL / VOL

False

Deasserted

VIH / VOH

True

Asserted

VIH / VOH

False

Deasserted

VIL / VOL

Note: *Values for VIL, VOL, VIH, and VOH are defined by individual product specifications.

CLOCK

GENERATOR

INTERNAL

DATA

BUS

SWITCH

EXTAL

PROGRAM

INTERRUPT

CONTROLLER

PROGRAM

DECODE

CONTROLLER

PROGRAM

ADDRESS

GENERATOR

YAB

XAB

PAB

YDB

XDB

PDB

GDB

MODA/IRQA

MODB/IRQB

DATA ALU

24X24+56->56-BIT MAC

TWO 56-BIT

ACCUMULATORS

BARREL SHIFTER

MODC/IRQC

PLL

OnCE™

HOST

INTER-

FACE

DAX

(SPDIF Tx.)

INTER-

FACE

X MEMORY

RAM

13K X 24

ROM

32K x 24

Y MEMORY

RAM

7K X 24

ROM

8K x 24

DDB

DAB

SIX CHANNELS

DMA UNIT

MEMORY EXPANSION AREA

PERIPHERAL

24 BITS BUS

EXPANSION AREA

JTAG

RESET

POWER

MNGMNT

PINIT/NMI

TRIPLE

TIMER

MODD/IRQD

DRAM &

SRAM BUS

INTERFACE

I - CACHE

EXTERNAL

ADDRESS

BUS

SWITCH

EXTERNAL

DATA BUS

SWITCH

ADDRESS

DATA

CONTROL

ESAI

INTER-

FACE

ESAI_1

ADDRESS

GENERATION

UNIT

24-BIT

DSP56300

Core

SHI

INTER-

FACE

PROGRAM

RAM/INSTR.

CACHE

3K x 24

PROGRAM ROM

40K x 24

Bootstrap ROM

192 x 24

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