MPC8280VRI datasheet(22/80 Pages) FREESCALE

22 / 80 page

MPC8280 PowerQUICC II™ Family Hardware Specifications, Rev. 1.7

Freescale Semiconductor

AC Electrical Characteristics

Figure 10 shows signal behavior for all parity modes (including ECC, RMW parity, and standard parity).

Figure 10. Parity Mode Diagram

Figure 11 shows signal behavior in MEMC mode.

Figure 11. MEMC Mode Diagram

NOTE

Generally, all MPC8280 bus and system output signals are driven from the rising

edge of the input clock (CLKin). Memory controller signals, however, trigger on

four points within a CLKin cycle. Each cycle is divided by four internal ticks: T1,

T2, T3, and T4. T1 always occurs at the rising edge, and T3 at the falling edge, of

CLKin. However, the spacing of T2 and T4 depends on the PLL clock ratio

selected, as shown in Table 13.

CLKin

DATA bus, ECC, and PARITY mode

Pipeline mode—

DP mode output signal

sp13

sp10

sp14a

sp10

Pipeline mode—

sp10

DP mode input signal

sp14

sp10

DATA bus, ECC, and PARITY mode

DP mode input signal

input signals

sp30

sp33b

sp13a

CLKin

V_CLK

Memory controller signals

sp34/sp30

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