MPC8280VRI datasheet(14/80 Pages) FREESCALE

14 / 80 page

MPC8280 PowerQUICC II™ Family Hardware Specifications, Rev. 1.7

Freescale Semiconductor

AC Electrical Characteristics

The following sections include illustrations and tables of clock diagrams, signals, and CPM outputs and inputs for

66.67/83.33/100 MHz devices. Note that AC timings are based on a 50-pf load for MAX Delay and 10-pf load for

MIN delay. Typical output buffer impedances are shown in Table 8.

Table 7. Estimated Power Dissipation for Various Configurations 1

Test temperature = 105

° C

Bus

(MHz)

CPM

Multiplication

Factor

CPM

(MHz)

CPU

Multiplication

Factor

CPU

(MHz)

PINT(W)

2, 3

PINT = IDD x VDD Watts

Values do not include I/O. Add the following estimates for active I/O based on the following bus speeds:

66.7 MHz = 0.45 W (nominal), 0.5 W (maximum)

83.3 MHz = 0.5W (nominal), 0.6 W (maximum)

100 MHz = 0.6 W (nominal), 0.7 W (maximum)

Vddl 1.5 Volts

Nominal

Maximum

66.67

2.5

166

3.5

233

0.95

1.0

66.67

2.5

166

266

1.0

1.05

66.67

200

266

1.05

1.1

66.67

3.5

233

4.5

300

1.05

1.15

83.33

250

333

1.25

1.35

83.33

250

4.5

375

1.3

1.4

83.33

3.5

292

417

1.45

1.55

100

300

400

1.5

1.6

100

300

4.5

450

1.55

1.65

Table 8. Output Buffer Impedances 1

These are typical values at 65° C. Impedance may vary by ±25% with process and temperature.

Output Buffers

Typical Impedance (

Ω)

60x bus

45 or 27 2

On silicon revision 0.0 (mask #: 0K49M), selectable impedance is not available. Impedance is set at 45

Ω.

On all other revisions, impedance value is selected through the SIUMCR[20,21]. Refer to the

MPC8280

PowerQUICC II Family Reference Manual.

Local bus

Memory controller

45 or 272

Parallel I/O

PCI

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