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MPC8555VTALF 数据表(PDF) 48 Page - Freescale Semiconductor, Inc

部件名 MPC8555VTALF
功能描述  PowerQUICC??III Integrated Communications Processor Hardware Specifications
PDF  88 Pages
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制造商  FREESCALE [Freescale Semiconductor, Inc]
网页  http://www.freescale.com
标志 FREESCALE - Freescale Semiconductor, Inc

MPC8555VTALF 数据表(HTML) 48 Page - Freescale Semiconductor, Inc

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MPC8555E PowerQUICC™ III Integrated Communications Processor Hardware Specifications, Rev. 4
48
Freescale Semiconductor
CPM
Figure 30. CPM I2C Bus Timing Diagram
The following two tables are examples of I2C AC parameters at I2C clock value of 100k and 400k
respectively.
Table 36. CPM I2C Timing (fSCL=100KHz)
Characteristic
Expression
Frequency = 100KHz
Unit
Min
Max
SCL clock frequency (slave)
fSCL
100
KHz
SCL clock frequency (master)
fSCL
-
100
KHz
Bus free time between transmissions
tSDHDL
4.7
-
μs
Low period of SCL
tSCLCH
4.7
-
μs
High period of SCL
tSCHCL
4-
μs
Start condition setup time
tSCHDL
2-
μs
Start condition hold time
tSDLCL
3-
μs
Data hold time
tSCLDX
2-
μs
Data setup time
tSDVCH
3-
μs
SDA/SCL rise time
tSRISE
-1
μs
SDA/SCL fall time (master)
tSFALL
-
303
ns
Stop condition setup time
tSCHDH
2-
μs
Table 37. CPM I2C Timing (fSCL=400KHz)
Characteristic
Expression
Frequency = 400KHz
Unit
Min
Max
SCL clock frequency (slave)
fSCL
400
KHz
SCL clock frequency (master)
fSCL
-400
KHz
Bus free time between transmissions
tSDHDL
1.2
-
μs
Low period of SCL
tSCLCH
1.2
-
μs
High period of SCL
tSCHCL
1-
μs
Start condition setup time
tSCHDL
420
-
ns
Start condition hold time
tSDLCL
630
-
ns
Data hold time
tSCLDX
420
-
ns
Data setup time
tSDVCH
630
-
ns
SDA/SCL rise time
tSRISE
-
250
ns
SDA/SCL fall time
tSFALL
-75
ns
Stop condition setup time
tSCHDH
420
-
ns
SCL
SDA
tSDHDL
tSCLCH
tSCHCL
tSCHDL
tSDLCL
tSCLDX
tSDVCH
tSRISE
tSFALL
tSCHDH



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