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© Andigilog, Inc. 2006
www.andigilog.com
October 2006 - 70A06010
aSC7621
Note: The following figures assume that Device Address 2Ch has been chosen by the user via address selection.
A7
A6
A5
A4
A3
A2
A1
A0
Start
SMBus Device Address Byte (2Ch)
Register Address Byte
A
A
ACK
from
aSC7621
ACK
from
aSC7621
SCL
SDA
0
1
9
1
9
A7
A6
A5
A4
A3
A2
A1
A0
Start
SMBus Device Address Byte (2Ch)
Register Address Byte
R/W
A
A
ACK
from
aSC7621
ACK
from
aSC7621
SCL
1
9
1
9
Stop
by
Master
1
9
D7
D6
D5
D4
D3
D2
D1
D0
Register Data Byte
A
ACK
from
aSC7621
Stop
By
Master
R/W
SDA
D7
D6
D5
D4
D3
D2
D1
D0
Re-start
Register Data Byte
A
N
R/W
SMBus Device Address Byte (2Ch)
ACK
from
aSC7621
NACK
from
Master
Stop
by
Master
Register Address
Pointer Set
(Figure 2.)
without stop by Master
+
1
9
1
9
SMBus Device Address Byte (2Ch)
ACK
from
aSC7621
NACK
from
Master
SCL
SDA
1
9
1
9
Stop
by
Master
D7
D6
D5
D4
D3
D2
D1
D0
Start
Register Data Byte
A
N
R/W
Figure 2 Register Address Pointer Set
Figure 3 Register Write
Figure 4 Register Read
Figure 5 Register Read When Read Address Already Set
0
1
1
1
0
S
0
0
1
1
1
0
S
0
0
1
1
1
0
S
0
0
1
1
1
0
S
0
0
0
0
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