MP8042 – HIGH CURRENT, DUAL CHANNEL POWER HALF-BRIDGE

INITIAL RELEASE – SPECIFICATIONS SUBJECT TO CHANGE

MP8042 Rev. 0.9

www.MonolithicPower.com

4

5/23/2006

MPS Proprietary Information. Unauthorized Photocopy and Duplication Prohibited.

© 2006 MPS. All Rights Reserved.

TM

PIN FUNCTIONS

Pin #

Name

Description

1

NC

No Connect.

2

AGND1 Analog Ground 1.

3

PWM1 Driver Logic Input 1. Drive PWM1 with the signal that controls the MP8042 OUT1. Drive PWM

high to turn on the high side switch; drive PWM low to turn on the low-side switch.

4

STBY

Standby Input. Default low (internal pull-down). If driven high, the output of drivers is

determined by the PWM1/2. If driven low, the output of both drivers is high impedance.

5

PWM2 Driver Logic Input 2. Drive PWM2 with the signal that controls the MP8042 OUT2. Drive PWM

high to turn on the high-side switch; drive PWM low to turn on the low-side switch.

6

FAULT

Fault Output. A low output at FAULT indicates that the MP8042 has detected an over

temperature, over current condition or the voltage to the driver is less than 5V. This output is

open drain.

7

SHDN

Shutdown Input. When low, both channels will be shut off.

8

AGND2 Analog Ground 2.

9

NC

No Connect.

10

VDR2

Gate Drive Supply Bypass 2. The voltage at VDR2 is supplied from an internal regulator from

VDD2. VDR2 powers the internal circuitry and internal MOSFET gate drive for the OUT2

stage. Bypass VDR2 to AGND2 with a 0.1µF to 10µF capacitor.

11

BST2

Bootstrap Supply 2. BST2 powers the high-side gate of the OUT2 stage. Connect a 0.1µF or

greater capacitor between BST2 and OUT2.

12

PGND2 Power Ground 2. Connect the exposed pad on bottom side to the ground plane.

13

OUT2

Switched Output 2. Connect the output LC filter to OUT2. OUT2 is valid approximately 100µs

after VDD2 goes high.

14

VDD2

Power Supply Input 2. Connect VDD2 to the positive side of the input power supply. Bypass

VDD2 to AGND2 as close to the IC as possible.

15

NC

No Connect.

16

VDD1

Power Supply Input 1. Connect VDD1 to the positive side of the input power supply. Bypass

VDD1 to GND1 as close to the IC as possible.

17

OUT1

Switched Output 1. Connect the output LC filter to OUT1. OUT1 is valid approximately 100µs

after VDD1 goes high.

18

PGND1 Power Ground 1. Connect the exposed pad on bottom side to the ground plane.

19

BST1

Bootstrap Supply 1. BST1 powers the high-side gate of the OUT1 stage. Connect a 0.1µF or

greater capacitor between BST1 and OUT1.

20

VDR1

Gate Drive Supply Bypass 1. The voltage at VDR1 is supplied from an internal regulator from

VDD1. VDR1 powers the internal circuitry and internal MOSFET gate drive for the OUT1

stage. Bypass VDR1 to AGND1 with a 0.1µF to 10µF capacitor.