15

LTC2609/LTC2619/LTC2629

26091929f

OPERATIO

C3

1ST DATA BYTE

Input Word (LTC2609)

Write Word Protocol for LTC2609/LTC2619/LTC1629

C2

C1

C0

A3

D13

D14

D15

S

WA

SLAVE ADDRESS

1ST DATA BYTE

D12 D11 D10 D9

D8

D7 D6

D5

D4

D3

D2

D1 D0

A

2ND DATA BYTE

A

3RD DATA BYTE

A

P

2ND DATA BYTE

INPUT WORD

3RD DATA BYTE

C3

1ST DATA BYTE

Input Word (LTC2619)

C2

C1

C0

A3

D11

D12

D13

D10 D9

D8

D7

D6

D5 D4

D3

D2

D1

D0

X

X

2ND DATA BYTE

3RD DATA BYTE

C3

1ST DATA BYTE

Input Word (LTC2629)

C2

C1

C0

A3

A2

A2

A2

A1

A1

A1

A0

A0

A0

D9

D10

D11

D8

D7

D6

D5

D4

D3 D2

D1

D0

X

X

X

X

2ND DATA BYTE

3RD DATA BYTE

loads a 16-bit data word from the 32-bit shift register into

the input register of the selected DAC, n. An update

operation copies the data word from the input register to

the DAC register. Once copied into the DAC register, the

data word becomes the active 16-, 14- or 12-bit input

code, and is converted to an analog voltage at the DAC

output. The update operation also powers up the selected

DAC if it had been in power-down mode. The data path and

registers are shown in the Block Diagram.

Figure 3

Power-Down Mode

For power-constrained applications, power-down mode

can be used to reduce the supply current whenever less

than four outputs are needed. When in power-down, the

buffer amplifiers, bias circuits and reference inputs are

disabled, and draw essentially zero current. The DAC

outputs are put into a high impedance state, and the

output pins are passively pulled to REFLO through

individual 90k resistors. Input- and DAC-register contents

are not disturbed during power down.

Any channel or combination of channels can be put into

power-down mode by using command 0100b in

combination with the appropriate DAC address, (n). The

16-bit data word is ignored. The supply current is reduced

by approximately 1/4 for each DAC powered down.

The effective resistance at REFx (Pins 3, 6, 12 and 15)

are at high impedance (typically > 1G

Ω) when the corre-

sponding DACs are powered down. Normal operation can

be resumed by executing any command which includes a

DAC update, as shown in Table 2.

The selected DAC is powered up as its voltage output is

updated. When a DAC which is in a powered-down state

is powered up and updated, normal settling is delayed. If

less than four DACs are in a powered-down state prior to

the update command, the power-up delay time is 5

µs.

If on the other hand, all four DACs are powered down,

Table 2

COMMAND*

C3

C2

C1

C0

0000

Write to Input Register n

0001

Update (Power Up) DAC Register n

0010

Write to Input Register n, Update (Power Up) All n

0011

Write to and Update (Power Up) n

0100

Power Down n

1111

No Operation

ADDRESS (n)*

A3

A2

A1

A0

0000

DAC A

0001

DAC B

0010

DAC C

0011

DAC D

1111

All DACs

*Command and address codes not shown are reserved and should not be used.