数据搜索系统,热门电子元器件搜索
  Chinese  ▼
ALLDATASHEETCN.COM

X  

LTC2609IGN 数据表(PDF) 4 Page - Linear Technology

部件名 LTC2609IGN
功能描述  Quad 16-/14-/12-Bit Rail-to-Rail DACs with I2C Interface
PDF  20 Pages
Scroll/Zoom Zoom In 100%  Zoom Out
制造商  LINER [Linear Technology]
网页  http://www.linear.com
标志 LINER - Linear Technology

LTC2609IGN 数据表(HTML) 4 Page - Linear Technology

  LTC2609IGN Datasheet HTML 1Page - Linear Technology LTC2609IGN Datasheet HTML 2Page - Linear Technology LTC2609IGN Datasheet HTML 3Page - Linear Technology LTC2609IGN Datasheet HTML 4Page - Linear Technology LTC2609IGN Datasheet HTML 5Page - Linear Technology LTC2609IGN Datasheet HTML 6Page - Linear Technology LTC2609IGN Datasheet HTML 7Page - Linear Technology LTC2609IGN Datasheet HTML 8Page - Linear Technology LTC2609IGN Datasheet HTML 9Page - Linear Technology Next Button
Zoom Inzoom in Zoom Outzoom out
 4 / 20 page
background image
4
LTC2609/LTC2619/LTC2629
26091929f
TI I G CHARACTERISTICS The denotes specifications which apply over the full operating temperature
range, otherwise specifications are at TA = 25°C. (See Figure 1) (Notes 8, 9)
ELECTRICAL C
C
HARA TERISTICS The denotes specifications which apply over the full operating
temperature range, otherwise specifications are at TA = 25°C. REFA = REFB = REFC = REFD = 4.096V (VCC = 5V), REFA = REFB =
REFC = REFD = 2.048V (VCC = 2.7V), REFLO = 0V, VOUT unloaded, unless otherwise noted.
SYMBOL
PARAMETER
CONDITIONS
MIN
TYP
MAX
MIN
TYP
MAX
MIN
TYP
MAX
UNITS
AC Performance
tS
Settling Time (Note 5)
±0.024% (±1LSB at 12 Bits)
7
7
7
µs
±0.006% (±1LSB at 14 Bits)
9
9
µs
±0.0015% (±1LSB at 16 Bits)
10
µs
Settling Time for 1LSB Step
±0.024% (±1LSB at 12 Bits)
2.7
2.7
2.7
µs
(Note 6)
±0.006% (±1LSB at 14 Bits)
4.8
4.8
µs
±0.0015% (±1LSB at 16 Bits)
5.2
µs
Voltage Output Slew Rate
0.7
0.7
0.7
V/
µs
Capacitive Load Driving
1000
1000
1000
pF
Glitch Impulse
At Midscale Transition
12
12
12
nV • s
Multiplying Bandwidth
180
180
180
kHz
en
Output Voltage Noise Density
At f = 1kHz
120
120
120
nV/
√Hz
At f = 10kHz
100
100
100
nV/
√Hz
Output Voltage Noise
0.1Hz to 10Hz
15
15
15
µVP-P
Note 1: Absolute maximum ratings are those values beyond which the life
of a device may be impaired.
Note 2: Linearity and monotonicity are defined from code kL to code
2N – 1, where N is the resolution and kL is given by kL = 0.016(2N/VREF),
rounded to the nearest whole code. For VREF = 4.096V and N = 16, kL =
256 and linearity is defined from code 256 to code 65,535.
Note 3: SDA, SCL at 0V or VCC, CA0, CA1 and CA2 floating.
Note 4: Inferred from measurement at code kL (see Note 2) and at full
scale.
Note 5: VCC = 5V, VREF = 4.096V. DAC is stepped 1/4 scale to 3/4 scale
and 3/4 scale to 1/4 scale. Load is 2k in parallel with 200pF to GND.
Note 6: VCC = 5V, VREF = 4.096V. DAC is stepped ±1LSB between half
scale and half scale – 1. Load is 2k in parallel with 200pF to GND.
Note 7: CB = capacitance of one bus line in pF.
Note 8: All values refer to VIH(MIN) and VIL(MAX) levels.
Note 9: These specifications apply to LTC2609/LTC2609-1,
LTC2619/LTC2619-1, LTC2629/LTC2629-1.
Note 10: DC crosstalk is measured with VCC = 5V, REFA = REFB = REFC =
REFD = 4.096V, with the measured DAC at midscale, unless otherwise
noted.
Note 11: RL = 2kΩ to GND or VCC.
Note 12: Guaranteed by design and not production tested.
LTC2629/LTC2629-1 LTC2619/LTC2619-1 LTC2609/LTC2609-1
SYMBOL
PARAMETER
CONDITIONS
MIN
TYP
MAX
UNITS
VCC = 2.7V to 5.5V
fSCL
SCL Clock Frequency
0
400
kHz
tHD(STA)
Hold Time (Repeated) Start Condition
0.6
µs
tLOW
Low Period of the SCL Clock Pin
1.3
µs
tHIGH
High Period of the SCL Clock Pin
0.6
µs
tSU(STA)
Set-Up Time for a Repeated Start Condition
0.6
µs
tHD(DAT)
Data Hold Time
0
0.9
µs
tSU(DAT)
Data Set-Up Time
100
ns
tr
Rise Time of Both SDA and SCL Signals
(Note 7)
20 + 0.1CB
300
ns
tf
Fall Time of Both SDA and SCL Signals
(Note 7)
20 + 0.1CB
300
ns
tSU(STO)
Set-Up Time for Stop Condition
0.6
µs
tBUF
Bus Free Time Between a Stop and Start Condition
1.3
µs
t1
Falling Edge of 9th Clock of the 3rd Input Byte
400
ns
to LDAC High or Low Transition
t2
LDAC Low Pulse Width
20
ns



Html Pages

1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20


数据表 下载

Go To PDF Page


链接网址



ALLDATASHEET是否为您带来帮助?  [ DONATE ] 

关于 Alldatasheet   |   广告服务   |   联系我们   |   隐私政策   |   数据表链接    |   链接交换   |   制造商名单
All Rights Reserved©Alldatasheet.com


Mirror Sites
English : Alldatasheet.com  |   English : Alldatasheet.net  |   Chinese : Alldatasheetcn.com  |   German : Alldatasheetde.com  |   Japanese : Alldatasheet.jp
Russian : Alldatasheetru.com  |   Korean : Alldatasheet.co.kr  |   Spanish : Alldatasheet.es  |   French : Alldatasheet.fr  |   Italian : Alldatasheetit.com
Portuguese : Alldatasheetpt.com  |   Polish : Alldatasheet.pl  |   Vietnamese : Alldatasheet.vn
Indian : Alldatasheet.in  |   Mexican : Alldatasheet.com.mx  |   British : Alldatasheet.co.uk  |   New Zealand : Alldatasheet.co.nz
Family Site : ic2ic.com  |   icmetro.com