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PI0256HSN 数据表(PDF) 3 Page - AMI SEMICONDUCTOR

部件名 PI0256HSN
功能描述  25-關m-Pitch Wide Aperture Spectroscopic Photodiode Arrays
PDF  8 Pages
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制造商  AMI [AMI SEMICONDUCTOR]
网页  http://www.amis.com
标志 AMI - AMI SEMICONDUCTOR

PI0256HSN 数据表(HTML) 3 Page - AMI SEMICONDUCTOR

  PI0256HSN Datasheet HTML 1Page - AMI SEMICONDUCTOR PI0256HSN Datasheet HTML 2Page - AMI SEMICONDUCTOR PI0256HSN Datasheet HTML 3Page - AMI SEMICONDUCTOR PI0256HSN Datasheet HTML 4Page - AMI SEMICONDUCTOR PI0256HSN Datasheet HTML 5Page - AMI SEMICONDUCTOR PI0256HSN Datasheet HTML 6Page - AMI SEMICONDUCTOR PI0256HSN Datasheet HTML 7Page - AMI SEMICONDUCTOR PI0256HSN Datasheet HTML 8Page - AMI SEMICONDUCTOR  
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PI0256HSN, PI0512HSN, PI1024HSN
Engineering Data Sheet
Page 3 of 8
March 13, 2002
0.0E+00
5.0E-05
1.0E-04
1.5E-04
2.0E-04
2.5E-04
100
300
500
700
900
Wavelength (nm)
QE=20%
QE=40%
QE=60%
QE=80%
Figure 4. Predicted spectral response.
The Quantum Efficiency (QE) can be calculated by
dividing the responsivity by the area of the sensor's
element and multiplying the resulting ratio by the
energy per photon in electron volts (eV).
The dark current is typically 0.2 pA at 25°C and varies
as function of temperature. The dark current will con-
tribute dark-signal charges and these charges will
increase linearly with integration time. The dark sig-
nal and the photo-generated signal combined result
in the total signal charge.
Selectable Charge Capacity
The HSN devices have the unique feature of having a
selectable charge capacity.
There is a bank of ca-
pacitors with one capacitor for each photodiode pixel.
When the capacitors are connected to the photodi-
odes, they give the photodiodes a charge capacity of
typically 65 pC. This large charge capacity is useful in
applications that demand high dynamic range and high
signal-to-noise ratios.
With the capacitors discon-
nected, the photodiodes have an intrinsic charge
capacity of typically 25 pC.
With a reduced capaci-
tance, the photodiode array can operate with a lower
reset (kTC) noise.
The ADDCAP pin is provided to control the connection
of the capacitors.
When ADDCAP is high, all the
capacitors are connected. When ADDCAP is low, all
the capacitors are disconnected. It is advised that all
the photodiodes are reset after each toggle of
ADDCAP. This is simply done by clocking one lines-
can of the photodiode array.
Anti-Blooming Circuit
Each photodiode pixel has a built-in anti-blooming
circuit structure. Without an anti-blooming circuit, it is
possible that a fraction of the excess charge from one
pixel will flow into neighboring pixels.
The anti-
blooming circuit prevents this by redirecting the excess
current into the anti-blooming drain before the photodi-
ode is too full. A self-biased anti-blooming gate sets
the level at which the charge begins to flow into the
drain. Think of it this way. If the photodiode were your
bathroom sink, then the anti-blooming circuit would be
your sink’s overflow drain.
The anti-blooming circuit may be disabled by ground-
ing the anti-blooming gate. This would in effect raise
the drain level.
Self-Scanning Circuit
Figure 5 shows a simplified electrically equivalent
circuit diagram of the photodiode array. An MOS read
switch connects every photodiode in the array to a
common output video line. Incident photons generate
electron charge that is collected on each imaging
photodiode while the switch is open. The shift register
is activated by the start pulse. A pulse propagates
through each shift register stage and activates the
MOS read switches sequentially. As the shift register
sequentially closes each read switch, the negative
stored charge, which is proportional in amount to the
light exposure, from the corresponding photodiode is
readout onto the video line, QOUT. Typically, an
external charge-integrating amplifier senses the nega-
tive output charge on the video line from each photodi-
ode pixel. The shift register continues scanning the
photodiodes in sequence, until the last shift register
stage is reach, at which time the fourth and last dummy
pixel is read out and end-of-scan (EOS) output is held
high for one clock cycle. The next start pulse can then
restart the shift register.



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