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PI0256HSN 数据表(PDF) 4 Page - AMI SEMICONDUCTOR |
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PI0256HSN 数据表(HTML) 4 Page - AMI SEMICONDUCTOR |
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4 / 8 page ![]() PI0256HSN, PI0512HSN, PI1024HSN Engineering Data Sheet Page 4 of 8 March 13, 2002 I/O Pins Besides the VSS and VDD supply pins, there are 9 functionally active I/O pins. Only two clocks, CLK and START, are required for controlling the timing of the sensor's video readout. One additional digital input, ADDCAP controls the bank of capacitors as described in the Selectable Charge Capacity section above. The digital output, EOS, marks the end of the line-scan. The charge output pin, QOUT, is typically connected to a charge-integrating amplifier that is biased to Vbias (see Recommended Operating Conditions section below). For normal anti-blooming operation, the ABG requires a 0.1-µF capacitor connected to VSS and the ABD is also biased to Vbias. Each temperature diode is operated with a small constant current that forward- biases its PN junction. By measuring the forward-bias voltage, one can track the silicon die temperature. The temperature diodes may be disabled by connecting their anodes to VSS. These I/Os are listed with their acronym designators and functional descriptions in the following Table 1. Table 1. Symbols and functions and I/O pins. Symbol Function and Description VSS Ground. VDD +5.0 Volts. START Start Pulse: Input to start the line scan. CLK Clock Pulse: Input to clock the shift register. ADDCAP Add Capacitors: Input that selects the bank of capacitors to increase charge capacity. EOS End Of Scan: Output from the shift register to indicate the completion of one line scan. QOUT Video Charge Output: Output from the photodiodes pixels. ABG Anti-Blooming Gate: Self-biased gate for setting anti-blooming level. Requires 0.1-µF connected to VSS. ABD Anti-Blooming Drain: Bias for anti-blooming drain. Set to Vbias. TD1 Temperature Diode 1: Anode of temperature diode 1. TD2 Temperature Diode 2: Anode of temperature diode 2. NC No Connection Figure 5. Simplified circuit diagram of a HSN photodiode array. The diagram does not include the capacitor bank and the anti-blooming circuitry. CLK ART TD1 SHIFT REGISTER EOS QOUT TD2 VSS |
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