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ADIN1300BCPZ-R7 数据表(PDF) 74 Page - Analog Devices |
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ADIN1300BCPZ-R7 数据表(HTML) 74 Page - Analog Devices |
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74 / 96 page  Data Sheet ADIN1300 REGISTER SUMMARY analog.com Rev. B | 74 of 96 Frame Checker Oversized Frame Count Register Address: 0x940F, Reset: 0x0000, Name: FC_OSZ_CNT This register is a latched copy of the oversized frame error counter register. This register is a count of received frames with a length greater than specified in frame checker maximum frame size (FC_MAX_FRM_SIZE register, Address 0x9407). When the receive error counter (RX_ERR_CNT register, Address 0x0014) is read, the oversized frame error counter register is latched, which ensures that the oversized frame error count and receive frame count are synchronized. Table 82. Bit Descriptions for FC_OSZ_CNT Bits Bit Name Description Reset Access [15:0] FC_OSZ_CNT Latched Copy of the Oversized Frame Error Counter. 0x0 R Frame Checker Undersized Frame Count Register Address: 0x9410, Reset: 0x0000, Name: FC_USZ_CNT This register is a latched copy of the undersized frame error counter register. This register is a count of received frames with a length less than 64 bytes. When the receive error counter (RX_ERR_CNT register, Address 0x0014) is read, the undersized frame error counter register is latched, which ensures that the undersized frame error count and receive frame count are synchronized. Table 83. Bit Descriptions for FC_USZ_CNT Bits Bit Name Description Reset Access [15:0] FC_USZ_CNT Latched Copy of the Undersized Frame Error Counter. 0x0 R Frame Checker Odd Nibble Frame Count Register Address: 0x9411, Reset: 0x0000, Name: FC_ODD_CNT This register is a latched copy of the odd nibble frame counter register. This register is a count of received frames with an odd number of nibbles in the frame in 100BASE-TX or 10BASE-T mode. When the receive error counter (RX_ERR_CNT register, Address 0x0014) is read, the odd nibble frame counter register is latched, which ensures that the odd nibble frame count and receive frame count are synchronized. Table 84. Bit Descriptions for FC_ODD_CNT Bits Bit Name Description Reset Access [15:0] FC_ODD_CNT Latched Copy of the Odd Nibble Counter. 0x0 R Frame Checker Odd Preamble Packet Count Register Address: 0x9412, Reset: 0x0000, Name: FC_ODD_PRE_CNT This register is a latched copy of the odd preamble packet counter register. This register is a count of received frames with an odd number of nibbles in the preamble in 100BASE-TX mode. When the receive error counter (RX_ERR_CNT register, Address 0x0014) is read, the odd preamble packet counter register is latched, which ensures that the odd preamble packet count and receive frame count are synchronized. Table 85. Bit Descriptions for FC_ODD_PRE_CNT Bits Bit Name Description Reset Access [15:0] FC_ODD_PRE_CNT Latched Copy of the Odd Preamble Packet Counter. 0x0 R Frame Checker Dribble Bits Frame Count Register Address: 0x9413, Reset: 0x0000, Name: FC_DRIBBLE_BITS_CNT |
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