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TDA4841PS 数据表(PDF) 18 Page - NXP Semiconductors |
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TDA4841PS 数据表(HTML) 18 Page - NXP Semiconductors |
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18 / 60 page  1999 Oct 25 18 Philips Semiconductors Product specification I2C-bus autosync deflection controller for PC monitors TDA4841PS Phase adjustments and corrections via PLL1 and PLL2 HPOS horizontal position (referenced to horizontal period) register HPOS = 0 −−13 − % register HPOS = 127 − 0 − % register HPOS = 255 − 13 − % HPINBAL horizontal pin unbalance correction via HPLL2 (referenced to horizontal period) register HPINBAL = 0; note 6 −−1.2 − % register HPINBAL = 63; note 6 − 1.2 − % register HPINBAL = 32; note 6 − 0.02 − % HPARAL horizontal parallelogram correction (referenced to horizontal period) register HPARAL = 0; note 6 −−1.2 − % register HPARAL = 63; note 6 − 1.2 − % register HPARAL = 32; note 6 − 0.02 − % HMOIRE relative modulation of horizontal position by 1 ⁄2 horizontal frequency; phase alternates with 1 ⁄2 vertical frequency register HMOIRE = 0; control bit MOD = 0 − 0 − % register HMOIRE = 63; control bit MOD = 0 − 0.02 − % moire cancellation off control bit MOD = 1 − 0 − % PLL2 phase detector: pins HFLB and HPLL2 φPLL2 PLL2 control (advance of horizontal drive with respect to middle of horizontal flyback) maximum advance; register HPINBAL = 32; register HPARAL = 32 36 −− % minimum advance; register HPINBAL = 32; register HPARAL = 32 − 7 − % Ictrl(PLL2) PLL2 control current − 75 −µA Φ PLL2 relative sensitivity of PLL2 phase shift related to horizontal period − 28 − mV/% VPROT(HPLL2)(max) maximum voltage for PLL2 protection mode/soft start − 4.6 − V Ich(PLL2) charge current for external capacitor during soft start VHPLL2 < 3.7 V − 1 −µA Idch(PLL2) discharge current for external capacitor during soft down VHPLL2 < 3.7 V −−1 −µA SYMBOL PARAMETER CONDITIONS MIN. TYP. MAX. UNIT |
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