TDA8002ATSLASH3 datasheet(8/28 Pages) PHILIPS

8 / 28 page

1997 Nov 04

Philips Semiconductors

Product speciﬁcation

IC card interface

TDA8002

Table 1

Clock circuitry deﬁnition

Notes

1. X = don’t care.

2. In low-power mode.

3. fint = 32 kHz in low-power mode.

MODE

CLKSEL

CLKDIV1

CLKDIV2

FREQUENCY

OF CLK

FREQUENCY

OF CLKOUT

HIGH

LOW

HIGH

LOW

⁄2fint

HIGH

LOW

⁄4fxtal

fxtal

HIGH

LOW

HIGH

⁄2fxtal

fxtal

HIGH

LOW

HIGH

STOP LOW

fxtal

HIGH

X(1)

STROBE

fxtal

LOW(2)

X(1)

STOP LOW

⁄2fint(3)

I/O circuitry

The three I/O transceivers are identical. The state is HIGH

for all I/O pins (i.e. I/O, I/OUC, AUX1, AUX1UC, AUX2 and

AUX2UC). Pin I/O is referenced to VCC and pin I/OUC to

VDD, thus ensuring proper operation in case VCC ≠ VDD.

The first side on which a falling edge is detected becomes

a master (input). An anti-latch circuitry first disables the

detection of the falling edge on the other side, which

becomes slave (output).

After a delay time td (about 50 ns), the logic 0 present on

the master side is transferred on the slave side.

When the input is back to HIGH level, a current booster is

turned on during the delay td on the output side and then

both sides are back to their idle state, ready to detect the

next logic 0 on any side.

In case of a conflict, both lines may remain LOW until the

software enables the lines to be HIGH. The anti-latch

circuitry ensures that the lines do not remain LOW if both

sides return HIGH, regardless of the prior conditions.

The maximum frequency on the lines is approximately

1 MHz.

Fig.6 Master and slave signals.

handbook, full pagewidth

MGD703

I/O

I/OUC

conflict

idle

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