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37LV128IT/SN 数据表(PDF) 4 Page - Microchip Technology |
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37LV128IT/SN 数据表(HTML) 4 Page - Microchip Technology |
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4 / 14 page ![]() 37LV36/65/128 DS21109F-page 4 2004 Microchip Technology Inc. FIGURE 11-1: READ CHARACTERISTICS TIMING TABLE 11-1: READ CHARACTERISTICS AC Testing Waveform: VIL = 0.2V; VIH = 3.0V AC Test Load: 50 pF VOL = VOL_MAX; VOH = VOH_MIN Symbol Parameter Limits 3.0V ≤ Vcc ≤ 6.0V Limits 4.5V ≤ Vcc ≤ 6.0V Units Conditions Min. Max. Min. Max. TOE OE to Data Delay — 45 — 45 ns TCE CE to Data Delay — 60 — 50 ns TCAC CLK to Data Delay — 200 — 60 ns TOH Data Hold from CE, OE or CLK 0 — 0 — ns TDF CE or OE to Data Float Delay — 50 — 50 ns Notes 1, 2 TLC CLK Low Time 100 — 25 — ns THC CLK High Time 100 — 25 — ns TSCE CE Set up Time to CLK (to guarantee proper counting) 40 — 25 — ns Note 1 TSCED CE setup time to CLK (to guarantee proper DATA read) 100 — 80 — ns THCE CE Hold Time to CLK (to guarantee proper counting) 0 — 0 — ns Note 1 THCED CE hold time to CLK (to guarantee proper DATA read) 50 — 0 — ns THOE OE High Time (Guarantees counters are Reset) 100 20 — ns CLK max Clock Frequency — 2.5 — 10 MHz Note 1: This parameter is periodically sampled and not 100% tested. 2: Float delays are measured with output pulled through 1k Ω to VLOAD = VCC/2. |
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