MCP3201_07 datasheet(12/28 Pages) MICROCHIP

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MCP3201

DS21290D-page 12

3.0

PIN DESCRIPTIONS

3.1

IN+

Positive analog input. This input can vary from IN- to

REF + IN-.

3.2

IN-

Negative analog input. This input can vary ±100 mV

from V

SS.

3.3

Chip Select/Shutdown (CS/SHDN)

The CS/SHDN pin is used to initiate communication

with the device when pulled low and will end a conver-

sion and put the device in low power standby when

pulled high. The CS/SHDN pin must be pulled high

between conversions.

3.4

Serial Clock (CLK)

The SPI clock pin is used to initiate a conversion and to

clock out each bit of the conversion as it takes place.

See Section 6.2 for constraints on clock speed.

3.5

Serial Data Output (DOUT)

The SPI serial data output pin is used to shift out the

results of the A/D conversion. Data will always change

on the falling edge of each clock as the conversion

takes place.

4.0

DEVICE OPERATION

The MCP3201 A/D Converter employs a conventional

SAR architecture. With this architecture, a sample is

acquired on an internal sample/hold capacitor for

1.5 clock cycles starting on the first rising edge of the

serial clock after CS has been pulled low. Following this

sample time, the input switch of the converter opens

and the device uses the collected charge on the inter-

nal sample and hold capacitor to produce a serial 12-bit

digital output code. Conversion rates of 100 ksps are

possible on the MCP3201. See Section 6.2 for informa-

tion on minimum clock rates. Communication with the

device is done using a 3-wire SPI-compatible interface.

4.1

Analog Inputs

The MCP3201 provides a single pseudo-differential

input. The IN+ input can range from IN- to V

REF

REF +IN-). The IN- input is limited to ±100 mV from the

SS rail. The IN- input can be used to cancel small sig-

nal common-mode noise which is present on both the

IN+ and IN- inputs.

For the A/D Converter to meet specification, the charge

holding capacitor (C

SAMPLE) must be given enough time

to acquire a 12-bit accurate voltage level during the

1.5 clock cycle sampling period. The analog input

model is shown in Figure 4-1.

In this diagram, it is shown that the source impedance

S) adds to the internal sampling switch (RSS) imped-

ance, directly affecting the time that is required to

charge the capacitor (C

SAMPLE). Consequently, a larger

source impedance increases the offset, gain, and inte-

gral linearity errors of the conversion.

Ideally, the impedance of the signal source should be

near zero. This is achievable with an operational ampli-

fier such as the MCP601, which has a closed loop out-

put impedance of tens of ohms. The adverse affects of

higher source impedances are shown in Figure 4-2.

If the voltage level of IN+ is equal to or less than IN-, the

resultant code will be 000h. If the voltage at IN+ is equal

to or greater than {[V

REF + (IN-)] - 1 LSB}, then the out-

put code will be FFFh. If the voltage level at IN- is more

than 1 LSB below V

SS, then the voltage level at the IN+

input will have to go below V

SS to see the 000h output

code.

Conversely, if IN- is more than 1 LSB above

Vss, then the FFFh code will not be seen unless the

IN+ input level goes above V

REF level.

4.2

Reference Input

The reference input (V

REF) determines the analog input

voltage range and the LSB size, as shown below.

As the reference input is reduced, the LSB size is

reduced accordingly. The theoretical digital output code

produced by the A/D Converter is a function of the ana-

log input signal and the reference input as shown

below.

where:

IN = analog input voltage = V(IN+) - V(IN-)

REF = reference voltage

When using an external voltage reference device, the

system designer should always refer to the manufac-

turer’s recommendations for circuit layout. Any instabil-

ity in the operation of the reference device will have a

direct effect on the operation of the A/D Converter.

LSB Size

REF

4096

-------------

Digital Output Code

4096*V

REF

------------------------

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