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MCP3201 数据表(PDF) 14 Page - Microchip Technology

部件名 MCP3201
功能描述  2.7V 12-Bit A/D Converter with SPI Serial Interface
PDF  28 Pages
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制造商  MICROCHIP [Microchip Technology]
网页  http://www.microchip.com
标志 MICROCHIP - Microchip Technology

MCP3201 数据表(HTML) 14 Page - Microchip Technology

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MCP3201
DS21290D-page 14
© 2007 Microchip Technology Inc.
5.0
SERIAL COMMUNICATIONS
Communication with the device is done using a stan-
dard SPI-compatible serial interface. Initiating commu-
nication with the MCP3201 begins with the CS going
low. If the device was powered up with the CS pin low,
it must be brought high and back low to initiate commu-
nication. The device will begin to sample the analog
input on the first rising edge after CS goes low. The
sample period will end in the falling edge of the second
clock, at which time the device will output a low null bit.
The next 12 clocks will output the result of the conver-
sion with MSB first, as shown in Figure 5-1. Data is
always output from the device on the falling edge of the
clock. If all 12 data bits have been transmitted and the
device continues to receive clocks while the CS is held
low, the device will output the conversion result LSB
first, as shown in Figure 5-2. If more clocks are pro-
vided to the device while CS is still low (after the LSB
first data has been transmitted), the device will clock
out zeros indefinitely.
FIGURE 5-1:
Communication with MCP3201 using MSB first Format.
FIGURE 5-2:
Communication with MCP3201 using LSB first Format.
CS
CLK
D
OUT
t
CYC
POWER
DOWN
T
SUCS
T
SAMPLE
t
CONV
t
DATA**
* After completing the data transfer, if further clocks are applied with CS low, the A/D Converter will output LSB first data, followed
by zeros indefinitely. See Figure below.
** t
DATA: during this time, the bias current and the comparator power down and the reference input becomes a high impedance
node, leaving the CLK running to clock out the LSB-first data or zeros.
T
CSH
NULL
BIT
B11
B10
B9
B8
B7
B6
B5
B4
B3
B2
B1
B0*
HI-Z
HI-Z
B11
B10
B9
B8
NULL
BIT
CS
CLK
D
OUT
t
CYC
POWER DOWN
t
SUCS
t
SAMPLE
t
CONV
t
DATA**
* After completing the data transfer, if further clocks are applied with CS low, the A/D Converter will output zeros indefinitely.
** t
DATA: during this time, the bias current and the comparator power down and the reference input becomes a high impedance
node, leaving the CLK running to clock out the LSB-first data or zeros.
t
CSH
NULL
BIT
B11 B10 B9
B8
B7
B6
B5
B4
B3
B2 B1 B0
HI-Z
B1
B2
B3
B4
B5
B6
B7
B8
B9 B10 B11*
HI-Z



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