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MCP2510-/ST 数据表(PDF) 47 Page - Microchip Technology |
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MCP2510-/ST 数据表(HTML) 47 Page - Microchip Technology |
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47 / 80 page ![]() © 2007 Microchip Technology Inc. DS21291F-page 47 MCP2510 REGISTER 7-1: CANINTE - INTERRUPT ENABLE REGISTER (ADDRESS: 2Bh) R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 MERRE WAKIE ERRIE TX2IE TX1IE TX0IE RX1IE RX0IE bit 7 bit 0 bit 7 MERRE: Message Error Interrupt Enable 1 = Interrupt on error during message reception or transmission 0 =Disabled bit 6 WAKIE: Wakeup Interrupt Enable 1 = Interrupt on CAN bus activity 0 =Disabled bit 5 ERRIE: Error Interrupt Enable (multiple sources in EFLG register) 1 = Interrupt on EFLG error condition change 0 =Disabled bit 4 TX2IE: Transmit Buffer 2 Empty Interrupt Enable 1 = Interrupt on TXB2 becoming empty 0 =Disabled bit 3 TX1IE: Transmit Buffer 1 Empty Interrupt Enable 1 = Interrupt on TXB1 becoming empty 0 =Disabled bit 2 TX0IE: Transmit Buffer 0 Empty Interrupt Enable 1 = Interrupt on TXB0 becoming empty 0 =Disabled bit 1 RX1IE: Receive Buffer 1 Full Interrupt Enable 1 = Interrupt when message received in RXB1 0 =Disabled bit 0 RX0IE: Receive Buffer 0 Full Interrupt Enable 1 = Interrupt when message received in RXB0 0 =Disabled Legend: R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’ -n = Value at POR ’1’ = Bit is set ’0’ = Bit is cleared x = Bit is unknown |
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