MCP3204-CISLASHP datasheet(13/34 Pages) MICROCHIP

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DS21298D-page 13

MCP3204/3208

3.0

PIN DESCRIPTIONS

The descriptions of the pins are listed in Table 3-1.

TABLE 3-1:

PIN FUNCTION TABLE

3.1

DGND

Digital ground connection to internal digital circuitry.

3.2

AGND

Analog ground connection to internal analog circuitry.

3.3

CH0 - CH7

Analog inputs for channels 0 - 7 for the multiplexed

inputs. Each pair of channels can be programmed to be

used as two independent channels in single-ended

mode or as a single pseudo-differential input, where

one channel is IN+ and one channel is IN. See

Section 4.1, “Analog Inputs”, and Section 5.0, “Serial

Communications”, for information on programming the

channel configuration.

3.4

Serial Clock (CLK)

The SPI clock pin is used to initiate a conversion and

clock out each bit of the conversion as it takes place.

See Section 6.2, “Maintaining Minimum Clock Speed”,

for constraints on clock speed.

3.5

Serial Data Input (D

IN)

The SPI port serial data input pin is used to load

channel configuration data into the device.

3.6

Serial Data Output (D

OUT)

The SPI serial data output pin is used to shift out the

results of the A/D conversion. Data will always change

on the falling edge of each clock as the conversion

takes place.

3.7

Chip Select/Shutdown (CS/SHDN)

The CS/SHDN pin is used to initiate communication

with the device when pulled low and will end a conver-

sion and put the device in low power standby when

pulled high. The CS/SHDN pin must be pulled high

between conversions.

4.0

DEVICE OPERATION

The MCP3204/3208 A/D converters employ a conven-

tional SAR architecture. With this architecture, a sam-

ple is acquired on an internal sample/hold capacitor for

1.5 clock cycles starting on the fourth rising edge of the

serial clock after the start bit has been received. Fol-

lowing this sample time, the device uses the collected

charge on the internal sample/hold capacitor to pro-

duce a serial 12-bit digital output code. Conversion

rates of 100 ksps are possible on the MCP3204/3208.

See Section 6.2, “Maintaining Minimum Clock Speed”,

for information on minimum clock rates. Communica-

tion with the device is accomplished using a 4-wire SPI-

compatible interface.

4.1

Analog Inputs

The MCP3204/3208 devices offer the choice of using

the analog input channels configured as single-ended

inputs or pseudo-differential pairs. The MCP3204 can

be configured to provide two pseudo-differential input

pairs or four single-ended inputs, while the MCP3208

can be configured to provide four pseudo-differential

input pairs or eight single-ended inputs. Configuration

is done as part of the serial command before each con-

version begins. When used in the pseudo-differential

mode, each channel pair (i.e., CH0 and CH1, CH2 and

CH3 etc.) is programmed to be the IN+ and IN- inputs

as part of the command string transmitted to the

device. The IN+ input can range from IN- to (VREF + IN-

). The IN- input is limited to ±100 mV from the VSS rail.

The IN- input can be used to cancel small signal com-

mon-mode noise which is present on both the IN+ and

IN- inputs.

When operating in the pseudo-differential mode, if the

voltage level of IN+ is equal to or less than IN-, the

resultant code will be 000h. If the voltage at IN+ is

equal to or greater than {[VREF + (IN-)] - 1 LSB}, then

the output code will be FFFh. If the voltage level at IN-

is more than 1 LSB below VSS, the voltage level at the

IN+ input will have to go below VSS to see the 000h

output code. Conversely, if IN- is more than 1 LSB

above VSS, then the FFFh code will not be seen unless

the IN+ input level goes above VREF level.

For the A/D converter to meet specification, the charge

holding capacitor (CSAMPLE) must be given enough

time to acquire a 12-bit accurate voltage level during

the 1.5 clock cycle sampling period. The analog input

model is shown in Figure 4-1.

Name

Function

VDD

+2.7V to 5.5V Power Supply

DGND

Digital Ground

AGND

Analog Ground

CH0-CH7

Analog Inputs

CLK

Serial Clock

DIN

Serial Data In

DOUT

Serial Data Out

CS/SHDN

Chip Select/Shutdown Input

VREF

Reference Voltage Input

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