MCP3204-CISLASHP datasheet(17/34 Pages) MICROCHIP

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DS21298D-page 17

MCP3204/3208

6.0

APPLICATIONS INFORMATION

6.1

Using the MCP3204/3208 with

Microcontroller (MCU) SPI Ports

With most microcontroller SPI ports, it is required to

send groups of eight bits. It is also required that the

microcontroller SPI port be configured to clock out data

on the falling edge of clock and latch data in on the ris-

ing edge. Because communication with the MCP3204/

3208 devices may not need multiples of eight clocks, it

will be necessary to provide more clocks than are

required. This is usually done by sending ‘leading

zeros’ before the start bit. As an example, Figure 6-1

and Figure 6-2 illustrate how the MCP3204/3208 can

be interfaced to a MCU with a hardware SPI port.

Figure 6-1 depicts the operation shown in SPI Mode

0,0, which requires that the SCLK from the MCU idles

in the ‘low’ state, while Figure 6-2 shows the similar

case of SPI Mode 1,1, where the clock idles in the ‘high’

state.

As is shown in Figure 6-1, the first byte transmitted to

the A/D converter contains five leading zeros before

the start bit. Arranging the leading zeros this way

allows the output 12 bits to fall in positions easily

manipulated by the MCU. The MSB is clocked out of

the A/D converter on the falling edge of clock number

12. Once the second eight clocks have been sent to the

device, the MCU’s receive buffer will contain three

unknown bits (the output is at high impedance for the

first two clocks), the null bit and the highest order four

bits of the conversion. Once the third byte has been

sent to the device, the receive register will contain the

lowest order eight bits of the conversion results.

Employing this method ensures simpler manipulation

of the converted data.

Figure 6-2 shows the same thing in SPI Mode 1,1,

which requires that the clock idles in the high state. As

with mode 0,0, the A/D converter outputs data on the

falling edge of the clock and the MCU latches data from

the A/D converter in on the rising edge of the clock.

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