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TDA8714M/7 数据表(PDF) 9 Page - NXP Semiconductors |
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TDA8714M/7 数据表(HTML) 9 Page - NXP Semiconductors |
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9 / 24 page ![]() 1997 Oct 29 9 Philips Semiconductors Product specification 8-bit high-speed analog-to-digital converter TDA8714 Notes to the characteristics 1. In addition to a good layout of the digital and analog ground, it is recommended that the rise and fall times of the clock must not be less than 1 ns. 2. Analog input voltages producing code 00 up to and including FF: a) VosB (voltage offset BOTTOM) is the difference between the analog input which produces data equal to 00 and the reference voltage BOTTOM (VRB) at Tamb =25 °C. b) VosT (voltage offset TOP) is the difference between VRT (reference voltage TOP) and the analog input which produces data outputs equal to FF at Tamb =25 °C. 3. Full-scale sine wave (fi = 4.43 MHz; fclk = 80 MHz). 4. The analog bandwidth is defined as the maximum input sine wave frequency which can be applied to the device. No glitches greater than 2 LSBs, neither any significant attenuation are observed in the reconstructed signal. 5. The analog input settling time is the minimum time required for the input signal to be stabilized after a sharp full-scale input (square-wave signal) in order to sample the signal and obtain correct output data. 6. Effective bits are obtained via a Fast Fourier Transform (FFT) treatment taking 8K acquisition points per equivalent fundamental period. The calculation takes into account all harmonics and noise up to half of the clock frequency (NYQUIST frequency). Conversion to signal-to-noise ratio: S/N = EB × 6.02 + 1.76 dB. 7. Intermodulation measured relative to either tone with analog input frequencies of 4.43 MHz and 4.53 MHz. The two input signals have the same amplitude and the total amplitude of both signals provides full scale to the converter. 8. Measurement carried out using video analyser VM700A where the video analog signal is reconstructed through a digital-to-analog converter. 9. Output data acquisition: the output data is available after the maximum delay time of td; in the event of 80 MHz clock operation, the hardware design must take into account the td and th limits with respect to the input characteristics of the acquisition circuit. |
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