Data Sheet

AD8351

Rev. D | Page 15 of 19

Due to package parasitic capacitance on the RG ports, high RG

values (low gain) cause high ac-peaking inside the pass band,

resulting in poor settling in the time domain. As an example,

when driving a 1 kΩ load, using 25 Ω for RIP reduces the peaking

by ~7 dB for RG equal to 200 Ω (AV = 10 dB) (see Figure 44).

Figure 44. Reducing Gain Peaking with Parasitic Suppressing Resistors

(RIP = 25 Ω, RL = 1 kΩ)

It is important to ensure that all I/O, ground, and RG port traces

be kept as short as possible. In addition, the ground plane must

be removed from under the package. Due to the inverse relation-

ship between the gain of the device and the value of the RG resistor,

any parasitic capacitance on the RG ports can result in gain-peaking

at high frequencies. Following the precautions outlined in Figure 45

helps to reduce parasitic board capacitance, thus extending the

bandwidth of the device and reducing potential peaking or

oscillation.

Figure 45. General Description of Recommended Board Layout for

High-Z Load Conditions (10-Lead MSOP Package)

TRANSMISSION LINE EFFECTS

As noted, stray transmission line capacitance, in combination

with package parasitics, can potentially form a resonant circuit

at high frequencies, resulting in excessive gain peaking. RF

transmission lines connecting the input and output networks

must be designed to minimize stray capacitance. The output

single-ended source impedance of the AD8351 is dynamically

set to a nominal value of 75 Ω. Therefore, for a matched load

termination, design the characteristic impedance of the output

transmission lines to be 75 Ω. In many situations, the final load

impedance may be relatively high, greater than 1 kΩ. It is sug-

gested that the board be designed as shown in Figure 45 for high

impedance load conditions. In most practical board designs, this

requires that the printed circuit board traces be dimensioned to

a small width (~5 mils) and that the underlying and adjacent

ground planes are far enough away to minimize capacitance.

Typically the driving source impedance into the device is below

and terminating resistors are used to prevent input reflections.

The transmission line must be designed to have the appropriate

characteristic impedance in the low-Z region. The high impedance

environment between the terminating resistors and device input

pins must not have ground planes underneath or near the signal

traces. Small parasitic suppressing resistors may be necessary at

the device input pins to help desensitize (de-Q) the resonant

effects of the device bond wires and surrounding parasitic board

capacitance. Typically, 25 Ω series resistors (size 0402) adequately

de-Q the input system without a significant decrease in ac

performance.

Figure 46 illustrates the value of adding input and output series

resistors to help desensitize the resonant effects of board parasitics.

Overshoot and undershoot can be significantly reduced with

the simple addition of RIP and ROP.

Figure 46. Step Response Characteristics With and Without Input and Output

Parasitic Suppression Resistors

10

100

1k

10k

FREQUENCY (MHz)

0

25

20

10

15

5

NO RIP

RIP = 25Ω

2

1

3

4

5

9

10

8

7

6

RIP

RIP

RT

RT

RG

ROP

ROP

HIGH-Z

AGND

AGND

COPLANAR

WAVEGUIDE

OR µSTRIP

01

234

TIME (ns)

–1.5

1.5

1.0

0

0.5

–1.0

–0.5

NO RIP OR ROP

RIP = ROP = 25Ω

ROP = 25Ω