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ADA4530-1ARZ-R7 数据表(PDF) 28 Page - Analog Devices

部件名 ADA4530-1ARZ-R7
功能描述  Femtoampere Input Bias Current Electrometer Amplifier
PDF  52 Pages
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制造商  AD [Analog Devices]
网页  http://www.analog.com
标志 AD - Analog Devices

ADA4530-1ARZ-R7 数据表(HTML) 28 Page - Analog Devices

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Data Sheet
ADA4530-1
THEORY OF OPERATION
analog.com
Rev. C | 28 of 52
The ADA4530-1 is an operational amplifier designed to interface
with the extremely high impedance sensors used in electrometer
applications.
A metal-oxide semiconductor field effect transistor (MOSFET) in-
put stage eliminates the gate leakage currents associated with
legacy junction gate field effect transistor (JFET) electrometers.
The ADA4530-1 achieves extremely low input bias currents while
simultaneously providing robust protection against ESD damage.
A unique ESD diode structure provides protection while also allow-
ing the diodes to be guarded to minimize leakage currents to
the input pins. The ADA4530-1 integrates the precision buffer that
guards internal ESD diode leakage paths. The output of this guard
buffer also connects to external pins, allowing the user to guard
external components against leakage currents.
The input bias current is determined by the accuracy of the guard
voltage applied across the ESD diodes. The offset voltages of the
amplifier and guard buffer set the accuracy of the guard voltage
and, therefore, the input bias current.
The ADA4530-1 uses Analog Devices, Inc., DigiTrim® technology to
achieve superior performance.
DigiTrim trims the offset voltage of the amplifier and guard buffer
to reject changes in the common-mode voltage, power supply volt-
age, and temperature. This technique significantly improves VOS,
CMRR, PSRR, and offset voltage temperature coefficient (TCVOS)
specifications.
Figure 99 shows the simplified schematic of the ADA4530-1. The
amplifier uses a three-stage architecture with a fully differential
input stage to achieve excellent dc performance specifications.
ESD STRUCTURE
The input ESD structure consists of Diode D1 to Diode D6.
The noninverting input is coupled to the guard pins (GRD) by the
D1 and D2 antiparallel diodes. The inverting input is coupled to the
guard pins by the D3 and D4 antiparallel diodes.
The guard pins are connected to the power supplies through Di-
ode D5 and Diode D6. During ESD events, the transient current
flows from the input pins through one of the antiparallel diodes
and harmlessly into the supplies through one of the power supply
diodes. During normal operation, the guard buffer (BUF1) forces the
voltage across the antiparallel diodes to 0 V. Resistor R1 shields
the guard buffer from potentially large capacitances connected to
the guard pins. Its value is nominally 1 kΩ.
INPUT STAGE
The input stage comprises a P-channel metal-oxide semiconductor
(PMOS) differential pair (M1, M2), folded cascode transistors (M5 to
M12), and current source (I1).
The ADA4530-1 achieves its high performance specifications by
using low voltage MOS devices for its differential inputs. These
low voltage MOS devices offer better 1/f noise and bandwidth per
unit current compared to high voltage devices. The input stage is
isolated from the high system voltages with proprietary protection
circuitry. This regulation circuitry protects the input devices from the
high supply voltages in which the amplifier can operate.
The proprietary high voltage protection circuitry in the ADA4530-1
operates to minimize the common-mode voltage changes seen by
the amplifier input stage for most of the input common-mode range.
This circuitry results in excellent disturbance rejection when operat-
ing in this preferred input common-mode range. The performance
benefits of operating within this preferred range are shown in the
VOS vs. VCM graphs (see Figure 16 to Figure 18), the small signal
CMRR vs. VCM graph (see Figure 21), and the small signal PSRR
vs. VCM graph (see Figure 54).
The input devices are protected from large differential input voltag-
es by the antiparallel ESD diodes (D1 to D4). The diodes can
conduct significant current when the differential voltage exceeds
700 mV. The user must ensure that the current flowing into the input
pins is limited to the absolute maximum of 10 mA.
Figure 99. Simplified Schematic



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