ADA4530-1ARZ-R7 datasheet(50/52 Pages) AD

50 / 52 page

Data Sheet

ADA4530-1

POWER SUPPLY RECOMMENDATIONS

analog.com

Rev. C | 50 of 52

Figure 135. Maximum Allowable Ripple at the Input of the LDOs to Bring

Spurs To Noise Floor Level (−120 dB)

LONG-TERM DRIFT

The stability of a precision signal path over its lifetime or between

calibration procedures is dependent on the long-term stability of the

analog components in the path, such as op amps, references, and

data converters. To help system designers predict the long-term

drift of circuits that use the ADA4530-1, Analog Devices measured

the offset voltage of multiple units for 10,000 hours (more than 13

months) using a high precision measurement system, including an

ultrastable oil bath. To replicate real-world system performance, the

devices under test (DUTs) were soldered onto an FR4 PCB using

a standard reflow profile (as defined in the JEDEC J-STD-020D

standard), as opposed to testing them in sockets. This manner

of testing is important because expansion and contraction of the

PCB can apply stress to the integrated circuit (IC) package and

contribute to shifts in the offset voltage.

The ADA4530-1 have extremely low long-term drift, as shown in

Figure 136. The red, blue, and green traces show sample units.

Note that the ADA4530-1 has a mean drift over 10,000 hours of

less than 0.5 µV, or less than 2% of its maximum specified offset

voltage of 40 µV at room temperature.

Figure 136. Measured Long-Term Drift of the ADA4530-1 Offset Voltage over

10,000 Hours

TEMPERATURE HYSTERESIS

In addition to stability over time as described in the Long-Term Drift

section, it is useful to know the temperature hysteresis, that is,

the stability vs. cycling of temperature. Hysteresis is an important

parameter because it tells the system designer how closely the

signal returns to its starting amplitude after the ambient temperature

changes and subsequent return to room temperature. Figure 137

shows the change in input offset voltage as the temperature cycles

three times from room temperature to 125°C to −40°C and back

to room temperature. The dotted line is an initial preconditioning

cycle to eliminate the original temperature induced offset shift from

exposure to production solder reflow temperatures. In the three full

cycles, the offset hysteresis is typically only 1.5 µV. The histogram

in Figure 138 shows that the hysteresis is larger when the device is

cycled through only a half cycle, from room temperature to 125°C

and back to room temperature.

Figure 137. Change in Offset Voltage over Three Full Temperature Cycles

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