ADA4932-1YCPZ-R7 datasheet(21/27 Pages) AD

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Data Sheet

ADA4932-1/ADA4932-2

APPLICATIONS INFORMATION

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Rev. F | 21 of 27

Similar to the case of a conventional op amp, the output noise

voltage densities can be estimated by multiplying the input-referred

terms at +IN and −IN by the appropriate output factor,

where:

GN= 2β1+β2 isthecircuitnoisegain.

β1= RG1RF1+RG1andβ2= RG2RF2+RG2arethefeedbackfactors.

When the feedback factors are matched, RF1/RG1 = RF2/RG2, β1 =

β2 = β, and the noise gain becomes

GN=1β=1+RFRG

Note that the output noise from VOCM goes to zero in this case. The

total differential output noise density, vnOD, is the root-sum-square

of the individual output noise terms.

vnOD= i=18vnOi2

Table 12 and Table 13 list several common gain settings, associat-

ed resistor values, input impedance, and output noise density for

both balanced and unbalanced input configurations.

IMPACT OF MISMATCHES IN THE FEEDBACK

NETWORKS

As previously mentioned, even if the external feedback networks

(RF/RG) are mismatched, the internal common-mode feedback loop

still forces the outputs to remain balanced. The amplitudes of the

signals at each output remain equal and 180° out of phase. The

input-to-output differential mode gain varies proportionately to the

feedback mismatch, but the output balance is unaffected.

The gain from the VOCM/VOCMx pin to VOUT, dm is equal to

2(β1 − β2)/(β1 + β2)

When β1 = β2, this term goes to zero and there is no differential

output voltage due to the voltage on the VOCM input (including

noise). The extreme case occurs when one loop is open and the

other has 100% feedback; in this case, the gain from VOCM input

to VOUT, dm is either +2 or −2, depending on which loop is closed.

The feedback loops are nominally matched to within 1% in most

applications, and the output noise and offsets due to the VOCM

input are negligible. If the loops are intentionally mismatched by a

large amount, it is necessary to include the gain term from VOCM

to VOUT, dm and account for the extra noise. For example, if β1 =

0.5 and β2 = 0.25, the gain from VOCM to VOUT, dm is 0.67. If

the VOCM/VOCMx pin is set to 2.5 V, a differential offset voltage is

present at the output of (2.5 V)(0.67) = 1.67 V. The differential

output noise contribution is (9.6 nV/√Hz)(0.67) = 6.4 nV/√Hz. Both

of these results are undesirable in most applications; therefore, it is

best to use nominally matched feedback factors.

Mismatched feedback networks also result in a degradation of the

ability of the circuit to reject input common-mode signals, much

the same as for a four-resistor difference amplifier made from a

conventional op amp.

As a practical summarization of the above issues, resistors of 1%

tolerance produce a worst-case input CMRR of approximately 40

dB, a worst-case differential-mode output offset of 25 mV due to

a 2.5 V VOCM input, negligible VOCM noise contribution, and no

significant degradation in output balance error.

CALCULATING THE INPUT IMPEDANCE FOR

AN APPLICATION CIRCUIT

The effective input impedance of a circuit depends on whether the

amplifier is being driven by a single-ended or differential signal

source. For balanced differential input signals, as shown in Figure

56, the input impedance (RIN, dm) between the inputs (+DIN and

−DIN) is RIN, dm = RG + RG = 2 × RG.

Figure 56. ADA4932-1/ADA4932-2 Configured for Balanced (Differential)

Inputs

For an unbalanced, single-ended input signal (see Figure 57), the

input impedance is

RIN,se= RG

1− RF

2× RG+RF

Figure 57. The ADA4932-1/ADA4932-2 with Unbalanced (Single-Ended) Input

The input impedance of the circuit is effectively higher than it is

for a conventional op amp connected as an inverter because a

fraction of the differential output voltage appears at the inputs as

a common-mode signal, partially bootstrapping the voltage across

the input resistor, RG. The common-mode voltage at the amplifier

input terminals can be easily determined by noting that the voltage

at the inverting input is equal to the noninverting output voltage

divided down by the voltage divider that is formed by RF and RG in

the lower loop. This voltage is present at both input terminals due

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