AD8099ACPZ-R2 datasheet(5/26 Pages) AD

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Data Sheet

AD8099

Rev. E | Page 5 of 26

ABSOLUTE MAXIMUM RATINGS

Table 3.

Parameter

Rating

Supply Voltage

12.6 V

Power Dissipation

See Figure 4

Differential Input Voltage

±1.8 V

Differential Input Current

±10mA

Storage Temperature Range

−

65°C to +125°C

Operating Temperature Range

−

40°C to +125°C

Lead Temperature (Soldering 10 sec)

300°C

Junction Temperature

150°C

Stresses at or above those listed under Absolute Maximum

Ratings may cause permanent damage to the product. This is a

stress rating only; functional operation of the product at these

or any other conditions above those indicated in the operational

section of this specification is not implied. Operation beyond

the maximum operating conditions for extended periods may

affect product reliability.

MAXIMUM POWER DISSIPATION

The maximum safe power dissipation in the AD8099 package is

limited by the associated rise in junction temperature (TJ) on

the die. The plastic encapsulating the die locally reaches the

junction temperature. At approximately 150°C, which is the

glass transition temperature, the plastic changes its properties.

Even temporarily exceeding this temperature limit may change

the stresses that the package exerts on the die, permanently

shifting the parametric performance of the AD8099. Exceeding

a junction temperature of 150°C for an extended period can

result in changes in silicon devices, potentially causing failure.

The still-air thermal properties of the package and PCB (θJA),

the ambient temperature (TA), and the total power dissipated in

the package (PD) determine the junction temperature of the die.

The junction temperature can be calculated as

(

)

The power dissipated in the package (PD) is the sum of the

quiescent power dissipation and the power dissipated in the

package due to the load drive for all outputs. The quiescent

power is the voltage between the supply pins (VS) times the

quiescent current (IS). Assuming the load (RL) is referenced to

midsupply, the total drive power is VS/2 × IOUT, some of which is

dissipated in the package and some in the load (VOUT × IOUT).

The difference between the total drive power and the load

power is the drive power dissipated in the package.

PD = Quiescent Power + (Total Drive Power − Load Power)

(

)

OUT

–













RMS output voltages should be considered. If RL is referenced to

VS−, as in single-supply operation, then the total drive power is

VS × IOUT. If the rms signal levels are indeterminate, consider the

worst case, when VOUT = VS/4 for RL to midsupply:

(

) (

)

In single-supply operation with RL referenced to VS–, worst case

is VOUT = VS/2.

Airflow increases heat dissipation, effectively reducing θJA. Also,

more metal directly in contact with the package leads from metal

traces, through holes, ground, and power planes reduce the θJA.

Soldering the exposed paddle to the ground plane significantly

reduces the overall thermal resistance of the package. Take care

to minimize parasitic capacitances at the input leads of high

speed op amps, as discussed in the PCB Layout section.

Figure 4 shows the maximum safe power dissipation in the

package versus the ambient temperature for the exposed paddle

(EPAD) SOIC-8 (70°C/W), and LFCSP (70°C/W), packages on

a JEDEC standard 4-layer board. θJA values are approximations.

AMBIENT TEMPERATURE (°C)

120

–40

–20

100

0.0

4.0

3.5

3.0

2.5

2.0

1.5

1.0

0.5

LFCSP AND SOIC

Figure 4. Maximum Power Dissipation

ESD CAUTION

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