AX88796ALF datasheet(13/68 Pages) ASIX

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AX88796ALF

3-in-1 Local Bus Fast Ethernet Controller

2.0 Signal Description

The following terms describe the AX88796A pin-out:

All pin names with the “/” suffix are asserted low.

The following abbreviations are used in following Tables.

Input

Internal Pull Up 100K ohm

Output

Internal Pull Down 90K ohm

I/O

Input/Output

Power Pin

TRI

TRI-state output

2.1 Local CPU Bus Interface Signals Group

SIGNAL

TYPE

PIN NO.

DESCRIPTION

SA[9:1],

SA[0] or NC

15,

12 – 4

System Address : Signals SA[9:0] are address bus input lines, which

lower I/O spaces on chip. When Motorola CPU type is selected, SA

[0] is useless.

/BHE

R/W

I/PU

Bus High Enable or Upper Data Strobe: Bus High Enable is active low

signal in some 16-bit application mode, which enable high bus

(SD[15:8]) active. When Motorola CPU type is selected, the pin is

active high for read operation, low for write operation.

SD[15:0]

I/O/PD

23 – 26,

29 – 33,

35 – 39,

41 – 42

System Data Bus: Signals SD[15:0] constitute the bi-directional data

bus.

IRQ

Interrupt Request: When ISA BUS or 80186 CPU modes is select.

IRQ is asserted high to indicate the host system that the chip requires

host software service. When MC68K or MCS-51 CPU mode is select.

/IRQ is asserted low to indicate the host system that the chip requires

host software service.

RDY/DTACK

TRI/PU

Ready: This signal is set low to insert wait states during Remote DMA

transfer.

/Dtack: When Motorola CPU type is selected, the pin is active low

inform CPU that data is accepted.

/CS

I/PU

128

Chip Select

When the /CS signal is asserted, the chip is selected.

/IORD

/UDS

I/PU

I/O Read: The host asserts /IORD to read data from AX88796A I/O

space. The signal also name as Upper Data Strobe (/UDS) for 68K

application mode.

/IOWR

/LDS

I/PU

I/O Write: The host asserts /IOWR to write data into AX88796A I/O

space. The signal also names as Lower Data Strobe (/LDS) for 68K

application mode.

/IOCS16

TRI/PU

123

I/O is 16 Bit Port: The /IOCS16 is asserted when the address at the

range corresponds to an I/O address to which the chip responds, and

the I/O port addressed is capable of 16-bit access.

AEN

/PSEN

I/PD

Address Enable: The signal is asserted when the address bus is

available for DMA cycle. When negated (low), AX88796A an I/O

slave device may respond to addresses and I/O command.

PSEN: This signal is active low for 8051 program access. For I/O

device, AX88796A, this signal is active high to access the chip. This

signal is for 8051 bus application only.

TAB - 1 Local CPU bus interface signals group

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