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AX88796ALF 数据表(PDF) 29 Page - ASIX Electronics Corporation |
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AX88796ALF 数据表(HTML) 29 Page - ASIX Electronics Corporation |
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29 / 68 page  29 AX88796ALF 3-in-1 Local Bus Fast Ethernet Controller Copyright © 2006-2013 ASIX Electronics Corporation. All rights reserved. COLLISION RECOVERY During transmission, the Buffer Management logic monitors the transmit circuitry to determine if a collision has occurred. If a collision is detected, the Buffer Management logic will reset the FIFO and restore the Transmit DMA pointers for retransmission of the packet. The COL bit will be set in the TSR and the NCR (Number of Collisions Register) will be incremented. If 15 retransmissions each result in a collision the transmission will be aborted and the ABT bit in the TSR will be set. Transmit Packet Assembly Format The following diagrams describe the format for how packets must be assembled prior to transmission for different byte ordering schemes. The various formats are selected in the Data Configuration Register and setting the CPU[1:0] pins for ISA, 80186, MC68K or MCS-51 mode. D15 D8 D7 D0 Destination Address 1 Destination Address 0 Destination Address 3 Destination Address 2 Destination Address 5 Destination Address 4 Source Address 1 Source Address 0 Source Address 3 Source Address 2 Source Address 5 Source Address 4 Type / Length 1 Type / Length 0 Data 1 Data 0 … … WTS = 1 in Data Configuration Register. This format is used with ISA or 80186 Mode. D15 D8 D7 D0 Destination Address 0 Destination Address 1 Destination Address 2 Destination Address 3 Destination Address 4 Destination Address 5 Source Address 0 Source Address 1 Source Address 2 Source Address 3 Source Address 4 Source Address 5 Type / Length 0 Type / Length 1 Data 0 Data 1 … … WTS = 1 in Data Configuration Register. This format is used with MC68K Mode. |
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