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AX88796ALF 数据表(PDF) 38 Page - ASIX Electronics Corporation

部件名 AX88796ALF
功能描述  10/100BASE 3-in-1 Local CPU Bus Fast Ethernet Controller with Embedded SRAM
PDF  68 Pages
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制造商  ASIX [ASIX Electronics Corporation]
网页  http://www.asix.com.tw
标志 ASIX - ASIX Electronics Corporation

AX88796ALF 数据表(HTML) 38 Page - ASIX Electronics Corporation

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AX88796ALF
3-in-1 Local Bus Fast Ethernet Controller
Copyright © 2006-2013 ASIX Electronics Corporation. All rights reserved.
5.1.3 Interrupt mask register (IMR) Offset 0FH (Write)
FIELD
NAME
DESCRIPTION
7
-
Reserved
6
RDCE
DMA Complete Interrupt Enable. Default “low” disabled.
5
CNTE
Counter Overflow Interrupt Enable. Default “low” disabled.
4
OVWE Overwrite Interrupt Enable. Default “low” disabled.
3
TXEE
Transmit Error Interrupt Enable. Default “low” disabled.
2
RXEE
Receive Error Interrupt Enable. Default “low” disabled.
1
PTXE
Packet Transmitted Interrupt Enable. Default “low” disabled.
0
PRXE
Packet Received Interrupt Enable. Default “low” disabled.
5.1.4 Data Configuration Register (DCR) Offset 0EH (Write)
FIELD
NAME
DESCRIPTION
7
-
Reserved
6:2
-
Reserved
1
-
Reserved
0
WTS
Word Transfer Select
0: Selects byte-wide DMA transfers.
1: Selects word-wide DMA transfers.
5.1.5 Transmit Configuration Register (TCR) Offset 0DH (Write)
FIELD
NAME
DESCRIPTION
7
FDU
Full Duplex:
This bit indicates the current media mode is Full Duplex or not. Ignore this setting when
using internal PHY. MAC duplex will be control by internal PHY duplex status.
0: Half duplex
1: Full duplex
6
PD
Pad Disable
0: Pad will be added when packet length less than 60.
1: Pad will not be added when packet length less than 60.
5
RLO
Retry of late collision
0: Don’t retransmit packet when late collision happens.
1: Retransmit packet when late collision happens.
4:3
-
Reserved
2:1
LB1, LB0 Encoded Loop-back Control
These encoded configuration bits set the type of loop-back that is to be performed.
LB1 LB0
Mode 0
0
0
Normal operation
Mode 1
0
1
Internal AX88796A loop-back
Mode 2
1
0
PHYcevisor loop-back
0
CRC
Inhibit CRC
0: CRC appended by transmitter.
1: CRC inhibited by transmitter.



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