ENC28J60-CSLASHSS datasheet(19/96 Pages) MICROCHIP

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Preliminary

DS39662B-page 17

ENC28J60

3.2

Ethernet Buffer

The Ethernet buffer contains transmit and receive

memory used by the Ethernet controller. The entire

buffer is 8 Kbytes, divided into separate receive and

transmit buffer spaces. The sizes and locations of

transmit and receive memory are fully programmable

by the host controller using the SPI interface.

The relationship of the buffer spaces is shown in

Figure 3-2.

3.2.1

RECEIVE BUFFER

The receive buffer constitutes a circular FIFO buffer

managed

hardware.

The

pairs

ERXSTH:ERXSTL and ERXNDH:ERXNDL serve as

Pointers to define the buffer’s size and location within

the memory. The byte pointed to by ERXST and the

byte pointed to by ERXND are both included in the

FIFO buffer.

As bytes of data are received from the Ethernet

interface, they are written into the receive buffer

sequentially. However, after the memory pointed to by

ERXND is written to, the hardware will automatically

write the next byte of received data to the memory

pointed to by ERXST. As a result, the receive hardware

will never write outside the boundaries of the FIFO.

The host controller may program the ERXST and

ERXND Pointers when the receive logic is not enabled.

The Pointers must not be modified while the receive

logic is enabled (ECON1.RXEN is set). If desired, the

Pointers may span the 1FFFh to 0000h memory

boundary; the hardware will still operate as a FIFO.

The ERXWRPTH:ERXWRPTL registers define a

location within the FIFO where the hardware will write

bytes that it receives. The Pointer is read-only and is

automatically updated by the hardware whenever a

new packet is successfully received. The Pointer is

useful for determining how much free space is

available within the FIFO.

The ERXRDPT registers define a location within the

FIFO where the receive hardware is forbidden to write

to. In normal operation, the receive hardware will write

data up to, but not including, the memory pointed to by

ERXRDPT. If the FIFO fills up with data and new data

continues to arrive, the hardware will not overwrite the

previously received data. Instead, the new data will be

thrown away and the old data will be preserved. In

order to continuously receive new data, the host con-

troller must periodically advance this Pointer whenever

it finishes processing some, or all, of the old received

data.

3.2.2

TRANSMIT BUFFER

Any space within the 8-Kbyte memory, which is not

programmed as part of the receive FIFO buffer, is

considered to be the transmit buffer. The responsibility

of managing where packets are located in the transmit

buffer belongs to the host controller. Whenever the host

controller decides to transmit a packet, the ETXST and

ETXND Pointers are programmed with addresses

specifying where, within the transmit buffer, the partic-

ular packet to transmit is located. The hardware does

not check that the start and end addresses do not

overlap with the receive buffer. To prevent buffer

corruption, the host controller must make sure to not

transmit a packet while the ETXST and ETXND

Pointers are overlapping the receive buffer, or while the

ETXND Pointer is too close to the receive buffer. See

Section 7.1

“Transmitting

Packets”

for

information.

3.2.3

READING AND WRITING TO

THE BUFFER

The Ethernet buffer contents are accessed from the

host controller though separate Read and Write Point-

ers (ERDPT and EWRPT) combined with the read

buffer

memory

and

write

buffer

memory

SPI

commands. While sequentially reading from the

receive buffer, a wrapping condition will occur at the

end of the receive buffer. While sequentially writing to

the buffer, no wrapping conditions will occur. See

Section 4.2.2 “Read Buffer Memory Command” and

Section 4.2.4 “Write Buffer Memory Command” for

more information.

3.2.4

DMA ACCESS TO THE BUFFER

The integrated DMA controller must read from the buffer

when calculating a checksum and it must read and write

to the buffer when copying memory. The DMA follows

the same wrapping rules that SPI accesses do. While it

sequentially reads, it will be subject to a wrapping condi-

tion at the end of the receive buffer. All writes it does will

not be subject to any wrapping conditions. See

Section 13.0 “Direct Memory Access Controller” for

more information.

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