ENC28J60T-CSLASHML datasheet(21/96 Pages) MICROCHIP

21 / 96 page

Preliminary

DS39662B-page 19

ENC28J60

3.3

PHY Registers

The PHY registers provide configuration and control of

the PHY module, as well as status information about its

operation. All PHY registers are 16 bits in width. There

are a total of 32 PHY addresses; however, only 9 loca-

tions are implemented. Writes to unimplemented

locations are ignored and any attempts to read these

locations will return ‘0’. All reserved locations should be

written as ‘0’; their contents should be ignored when

read.

Unlike the ETH, MAC and MII control registers, or the

buffer memory, the PHY registers are not directly

accessible through the SPI control interface. Instead,

access is accomplished through a special set of MAC

control registers that implement Media Independent

Interface Management (MIIM). These control registers

are referred to as the MII registers. The registers that

control access to the PHY registers are shown in

3.3.1

READING PHY REGISTERS

When a PHY register is read, the entire 16 bits are

obtained.

To read from a PHY register:

Write the address of the PHY register to read

from into the MIREGADR register.

Set the MICMD.MIIRD bit. The read operation

begins and the MISTAT.BUSY bit is set.

Wait 10.24

μs. Poll the MISTAT.BUSY bit to be

certain that the operation is complete. While

busy, the host controller should not start any

MIISCAN operations or write to the MIWRH

When the MAC has obtained the register

contents, the BUSY bit will clear itself.

Clear the MICMD.MIIRD bit.

Read the desired data from the MIRDL and

MIRDH registers. The order that these bytes are

accessed is unimportant.

3.3.2

WRITING PHY REGISTERS

When a PHY register is written to, the entire 16 bits is

written at once; selective bit writes are not imple-

mented. If it is necessary to reprogram only select bits

in the register, the controller must first read the PHY

data back to the PHY register.

To write to a PHY register:

Write the address of the PHY register to write to

into the MIREGADR register.

Write the lower 8 bits of data to write into the

MIWRL register.

Write the upper 8 bits of data to write into the

MIWRH register. Writing to this register auto-

matically begins the MIIM transaction, so it must

be written to after MIWRL. The MISTAT.BUSY

bit becomes set.

The PHY register will be written after the MIIM opera-

tion completes, which takes 10.24

μs. When the write

operation has completed, the BUSY bit will clear itself.

The host controller should not start any MIISCAN or

MIIRD operations while busy.

3.3.3

SCANNING A PHY REGISTER

The MAC can be configured to perform automatic

back-to-back read operations on a PHY register. This

can significantly reduce the host controller complexity

when periodic status information updates are desired.

To perform the scan operation:

Write the address of the PHY register to read

from into the MIREGADR register.

Set the MICMD.MIISCAN bit. The scan opera-

tion begins and the MISTAT.BUSY bit is set. The

first read operation will complete after 10.24

μs.

Subsequent reads will be done at the same

interval until the operation is cancelled. The

MISTAT.NVALID bit may be polled to determine

when the first read operation is complete.

After setting the MIISCAN bit, the MIRDL and MIRDH

registers will automatically be updated every 10.24

μs.

There is no status information which can be used to

determine when the MIRD registers are updated. Since

the host controller can only read one MII register at a

time through the SPI, it must not be assumed that the

values of MIRDL and MIRDH were read from the PHY

at exactly the same time.

When the MIISCAN operation is in progress, the host

controller must not attempt to write to MIWRH or start

an MIIRD operation. The MIISCAN operation can be

cancelled by clearing the MICMD.MIISCAN bit and

then polling the MISTAT.BUSY bit. New operations may

be started after the BUSY bit is cleared.

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