ENC28J60T-CSLASHML datasheet(17/96 Pages) MICROCHIP

17 / 96 page

Preliminary

DS39662B-page 15

ENC28J60

3.1.1

ECON1 REGISTER

The ECON1 register, shown in Register 3-1, is used to

control the main functions of the ENC28J60. Receive

enable, transmit request, DMA control and bank select

bits can all be found in ECON1.

ECON1: ETHERNET CONTROL REGISTER 1

R/W-0

TXRST

RXRST

DMAST

CSUMEN

TXRTS

RXEN

BSEL1

BSEL0

bit 7

bit 0

Legend:

R = Readable bit

W = Writable bit

U = Unimplemented bit, read as ‘0’

-n = Value at POR

‘1’ = Bit is set

‘0’ = Bit is cleared

x = Bit is unknown

bit 7

TXRST: Transmit Logic Reset bit

= Transmit logic is held in Reset

= Normal operation

bit 6

RXRST: Receive Logic Reset bit

= Receive logic is held in Reset

= Normal operations

bit 5

DMAST: DMA Start and Busy Status bit

= DMA copy or checksum operation is in progress

= DMA hardware is Idle

bit 4

CSUMEN: DMA Checksum Enable bit

= DMA hardware calculates checksums

= DMA hardware copies buffer memory

bit 3

TXRTS: Transmit Request to Send bit

= The transmit logic is attempting to transmit a packet

= The transmit logic is Idle

bit 2

RXEN: Receive Enable bit

= Packets which pass the current filter configuration will be written into the receive buffer

= All packets received will be ignored

bit 1-0

BSEL1:BSEL0: Bank Select bits

= SPI accesses registers in Bank 3

= SPI accesses registers in Bank 2

= SPI accesses registers in Bank 1

= SPI accesses registers in Bank 0

ENC28J60T-C/ML 数据表(PDF) 17 Page - Microchip Technology

ENC28J60T-C/ML 数据表(HTML) 17 Page - Microchip Technology

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