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ENC28J60T-C/ML 数据表(PDF) 66 Page - Microchip Technology |
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ENC28J60T-C/ML 数据表(HTML) 66 Page - Microchip Technology |
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66 / 96 page  ENC28J60 DS39662B-page 64 Preliminary © 2006 Microchip Technology Inc. 12.1 INT Interrupt Enable (INTIE) The INT Interrupt Enable bit (INTIE) is a global enable bit which allows the following interrupts to drive the INT pin: • Receive Error Interrupt (RXERIF) • Transmit Error Interrupt (TXERIF) • Transmit Interrupt (TXIF) • Link Change Interrupt (LINKIF) • DMA Interrupt (DMAIF) • Receive Packet Pending Interrupt (PKTIF) When any of the above interrupts are enabled and generated, the virtual bit, INT in the ESTAT register (Register 12-1), will be set to ‘1’. If EIE.INTIE is ‘1’, the INT pin will be driven low. 12.1.1 INT INTERRUPT REGISTERS The registers associated with the INT interrupts are shown in Register 12-2, Register 12-3, Register 12-4 and Register 12-5. REGISTER 12-1: ESTAT: ETHERNET STATUS REGISTER R-0 R/C-0 R-0 R/C-0 U-0 R-0 R/C-0 R/W-0 INT BUFER r LATECOL — RXBUSY TXABRT CLKRDY bit 7 bit 0 Legend: R = Readable bit C = Clearable bit U = Unimplemented bit, read as ‘0’ -n = Value at POR ‘1’ = Bit is set ‘0’ = Bit is cleared x = Bit is unknown bit 7 INT: INT Interrupt Flag bit 1 = INT interrupt is pending 0 = No INT interrupt is pending bit 6 BUFER: Ethernet Buffer Error Status bit 1 = An Ethernet read or write has generated a buffer error (overrun or underrun) 0 = No buffer error has occurred bit 5 Reserved: Read as ‘0’ bit 4 LATECOL: Late Collision Error bit 1 = A collision occurred after 64 bytes had been transmitted 0 = No collisions after 64 bytes have occurred bit 3 Unimplemented: Read as ‘0’ bit 2 RXBUSY: Receive Busy bit 1 = Receive logic is receiving a data packet 0 = Receive logic is Idle bit 1 TXABRT: Transmit Abort Error bit 1 = The transmit request was aborted 0 = No transmit abort error bit 0 CLKRDY: Clock Ready bit 1 = OST has expired; PHY is ready 0 = OST is still counting; PHY is not ready |
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