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PIC16F-E/ML 数据表(PDF) 39 Page - Microchip Technology |
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PIC16F-E/ML 数据表(HTML) 39 Page - Microchip Technology |
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39 / 178 page ![]() © 2007 Microchip Technology Inc. DS40044F-page 37 PIC16F627A/628A/648A FIGURE 5-9: BLOCK DIAGRAM OF RB1/RX/DT PIN FIGURE 5-10: BLOCK DIAGRAM OF RB2/TX/CK PIN Data Latch TRIS Latch RD TRISB Q D Q CK Q D Q CK 1 0 WR PORTB WR TRISB Schmitt Trigger Peripheral OE(1) Data Bus SPEN USART Data Output USART Receive Input RBPU VDD P EN QD VDD VSS Note 1: Peripheral OE (output enable) is only active if peripheral select is active. RD PORTB RX/DT RB1/ TTL Input Buffer Weak Pull-up Data Latch TRIS Latch RD TRISB Q D Q CK Q D Q CK 1 0 WR PORTB WR TRISB Schmitt Trigger Peripheral OE(1) Data Bus SPEN USART TX/CK Output USART Slave Clock In RBPU VDD P EN QD VDD VSS Note 1: Peripheral OE (output enable) is only active if peripheral select is active. RD PORTB TTL Input Buffer RB2/ TX/CK Weak Pull-up |
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