PIC16F-ESLASHML datasheet(85/178 Pages) MICROCHIP

85 / 178 page

DS40044F-page 83

PIC16F627A/628A/648A

12.3

USART Address Detect Function

12.3.1

USART 9-BIT RECEIVER WITH

ADDRESS DETECT

When the RX9 bit is set in the RCSTA register, 9 bits

are received and the ninth bit is placed in the RX9D bit

of the RCSTA register. The USART module has a

special provision for multiprocessor communication.

Multiprocessor communication is enabled by setting

the ADEN bit (RCSTA<3>) along with the RX9 bit. The

port is now programmed such that when the last bit is

received, the contents of the Receive Shift Register

(RSR) are transferred to the receive buffer, the ninth bit

of the RSR (RSR<8>) is transferred to RX9D, and the

receive interrupt is set if and only if RSR<8> = 1. This

feature can be used in a multiprocessor system as

follows:

A master processor intends to transmit a block of data

to one of many slaves. It must first send out an address

byte that identifies the target slave. An address byte is

identified by setting the ninth bit (RSR<8>) to a ‘1’

(instead of a ‘0’ for a data byte). If the ADEN and RX9

bits are set in the slave’s RCSTA register, enabling

multiprocessor communication, all data bytes will be

ignored. However, if the ninth received bit is equal to a

‘1’, indicating that the received byte is an address, the

slave will be interrupted and the contents of the RSR

allows the slave to be interrupted only by addresses, so

that the slave can examine the received byte to see if it

is being addressed. The addressed slave will then clear

its ADEN bit and prepare to receive data bytes from the

master.

When ADEN is enabled (= 1), all data bytes are

ignored. Following the Stop bit, the data will not be

loaded into the receive buffer, and no interrupt will

occur. If another byte is shifted into the RSR register,

the previous data byte will be lost.

The ADEN bit will only take effect when the receiver is

configured in 9-bit mode (RX9 = 1). When ADEN is

disabled (= 0), all data bytes are received and the 9th

bit can be used as the parity bit.

The receive block diagram is shown in Figure 12-4.

Reception

enabled

setting

bit

CREN

(RCSTA<4>).

12.3.1.1

Setting up 9-bit mode with Address

Detect

Follow these steps when setting up Asynchronous

Reception with Address Detect Enabled:

TRISB<1> and TRISB<2> should both be set to

‘1’ to configure the RB1/RX/DT and RB2/TX/CK

pins as inputs. Output drive, when required, is

controlled by the peripheral circuitry.

Initialize the SPBRG register for the appropriate

baud rate. If a high-speed baud rate is desired,

set bit BRGH.

Enable asynchronous communication by setting

or clearing bit SYNC and setting bit SPEN.

If interrupts are desired, then set enable bit

RCIE.

Set bit RX9 to enable 9-bit reception.

Set ADEN to enable address detect.

Enable the reception by setting enable bit CREN

or SREN.

Flag bit RCIF will be set when reception is

complete and an interrupt will be generated if

enable bit RCIE was set.

Read the 8-bit received data by reading the

RCREG register to determine if the device is

being addressed.

10. If an OERR error occurred, clear the error by

clearing enable bit CREN if it was already set.

11. If the device has been addressed (RSR<8> = 1

with address match enabled), clear the ADEN

and RCIF bits to allow data bytes and address

bytes to be read into the receive buffer and

interrupt the CPU.

TABLE 12-8:

REGISTERS ASSOCIATED WITH ASYNCHRONOUS RECEPTION

Address

Name

Bit 7

Bit 6

Bit 5

Bit 4

Bit 3

Bit 2

Bit 1

Bit 0

Value on

POR

Value on

all other

Resets

0Ch

PIR1

EEIF

CMIF

RCIF

TXIF

—

CCP1IF TMR2IF TMR1IF 0000 -000

0000 -000

18h

RCSTA

SPEN

RX9

SREN

CREN

ADEN

FERR

OERR

RX9D

0000 000x

1Ah

RCREG USART Receive Data Register

0000 0000

8Ch

PIE1

EEIE

CMIE

RCIE

TXIE

—

CCP1IE TMR2IE TMR1IE 0000 -000

0000 -000

98h

TXSTA

CSRC

TX9

TXEN

SYNC

—BRGH

TRMT

TX9D

0000 -010

99h

SPBRG Baud Rate Generator Register

0000 0000

Legend:

= unknown, - = unimplemented locations read as ‘0’. Shaded cells are not used for asynchronous

reception.

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