PIC16F-ESLASHML datasheet(92/178 Pages) MICROCHIP

92 / 178 page

PIC16F627A/628A/648A

DS40044F-page 90

13.1

EEADR

The PIC16F648A EEADR register addresses 256

bytes of data EEPROM. All eight bits in the register

(EEADR<7:0>) are required.

The PIC16F627A/628A EEADR register addresses

only the first 128 bytes of data EEPROM so only seven

of the eight bits in the register (EEADR<6:0>) are

required. The upper bit is address decoded. This

means that this bit should always be ‘0’ to ensure that

the address is in the 128 byte memory space.

13.2

EECON1 and EECON2 Registers

EECON1 is the control register with four low order bits

physically implemented. The upper-four bits are non-

existent and read as ‘0’s.

Control bits RD and WR initiate read and write,

respectively. These bits cannot be cleared, only set, in

software. They are cleared in hardware at completion

of the read or write operation. The inability to clear the

WR bit in software prevents the accidental, premature

termination of a write operation.

The WREN bit, when set, will allow a write operation.

On power-up, the WREN bit is clear. The WRERR bit is

set when a write operation is interrupted by a MCLR

Reset or a WDT Time-out Reset during normal

operation. In these situations, following Reset, the user

can check the WRERR bit and rewrite the location. The

data and address will be unchanged in the EEDATA

and EEADR registers.

Interrupt flag bit EEIF in the PIR1 register is set when

write is complete. This bit must be cleared in software.

EECON2 is not a physical register. Reading EECON2

will read all ‘0’s. The EECON2 register is used

exclusively in the data EEPROM write sequence.

EECON1 – EEPROM CONTROL REGISTER 1 (ADDRESS: 9Ch)

U-0

R/W-x

R/W-0

R/S-0

—

WRERR

WREN

bit 7

bit 0

bit 7-4

Unimplemented: Read as ‘0’

bit 3

WRERR: EEPROM Error Flag bit

= A write operation is prematurely terminated (any MCLR Reset, any WDT Reset during

normal operation or BOR Reset)

= The write operation completed

bit 2

WREN: EEPROM Write Enable bit

= Allows write cycles

= Inhibits write to the data EEPROM

bit 1

WR: Write Control bit

= initiates a write cycle. (The bit is cleared by hardware once write is complete. The WR bit

can only be set (not cleared) in software.

= Write cycle to the data EEPROM is complete

bit 0

RD: Read Control bit

= Initiates an EEPROM read (read takes one cycle. RD is cleared in hardware. The RD bit

can only be set (not cleared) in software).

= Does not initiate an EEPROM read

Legend:

R = Readable bit

W = Writable bit

U = Unimplemented bit, read as ‘0’

-n = Value at POR

‘1’ = Bit is set

‘0’ = Bit is cleared

x = Bit is unknown

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