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CDB4349 数据表(PDF) 13 Page - Cirrus Logic |
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CDB4349 数据表(HTML) 13 Page - Cirrus Logic |
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13 / 40 page ![]() DS782F1 13 CS4349 SWITCHING SPECIFICATIONS - SERIAL AUDIO INTERFACE Inputs: Logic 0 = GND; Logic 1 = VLS; CL =20pF. Parameters Symbol Min Max Units 3.14 V ≤ VA ≤ 5.25 V and 1.35 V ≤ VLS ≤ 5.25 V RMCK Output Frequency (Note ) 7.680 55.3 MHz RMCK Output Duty Cycle 45 55 % Input Sample Rate Single-Speed Mode 30 54 Double-Speed Mode Fs 60 108 kHz Quad-Speed Mode 120 216 LRCK Duty Cycle (Non-TDM Mode) 40 60 % SDIN Setup Time Before SCLK Rising Edge tds 1- ns SDIN Hold Time After SCLK Rising Edge tdh 1- ns 4.75 V ≤ VA ≤ 5.25 V and 3.14 V ≤ VLS ≤ 5.25 V SCLK Frequency -55.3 MHz SCLK High Time tsckh 6- ns SCLK Low Time tsckl 6- ns Non-TDM Mode (refer to Figure 6) LRCK Edge to SCLK Rising Edge tlcks 11 - ns SCLK Rising Edge to LRCK Edge tlckd 1- ns TDM Mode (refer to Figure 7) LRCK High Time tlrckh 6- ns SCLK Rising to LRCK Falling Edge tfsh 3- ns LRCK Rising Edge to SCLK Rising Edge tfss 1- ns 3.14 V ≤ VA < 4.75 V or 1.35 V ≤ VLS < 3.14 V SCLK Frequency -27.7 MHz SCLK High Time tsckh 11 - ns SCLK Low Time tsckl 11 - ns Non-TDM Mode (refer to Figure 6) LRCK Edge to SCLK Rising Edge tlcks 16 - ns SCLK Rising Edge to LRCK Edge tlckd 1- ns TDM Mode (refer to Figure 7) LRCK High Time tlrckh 25 - ns SCLK Rising to LRCK Falling Edge tfsh 8- ns LRCK Rising Edge to SCLK Rising Edge tfss 1- ns |
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