数据搜索系统,热门电子元器件搜索
  Chinese  ▼
ALLDATASHEETCN.COM

X  

CDB4349 数据表(PDF) 21 Page - Cirrus Logic

部件名 CDB4349
功能描述  192 kHz DAC w/ Volume Control and 1 Vrms @ 3.3 V
PDF  40 Pages
Scroll/Zoom Zoom In 100%  Zoom Out
制造商  CIRRUS [Cirrus Logic]
网页  http://www.cirrus.com
标志 CIRRUS - Cirrus Logic

CDB4349 数据表(HTML) 21 Page - Cirrus Logic

Back Button CDB4349 Datasheet HTML 17Page - Cirrus Logic CDB4349 Datasheet HTML 18Page - Cirrus Logic CDB4349 Datasheet HTML 19Page - Cirrus Logic CDB4349 Datasheet HTML 20Page - Cirrus Logic CDB4349 Datasheet HTML 21Page - Cirrus Logic CDB4349 Datasheet HTML 22Page - Cirrus Logic CDB4349 Datasheet HTML 23Page - Cirrus Logic CDB4349 Datasheet HTML 24Page - Cirrus Logic CDB4349 Datasheet HTML 25Page - Cirrus Logic Next Button
Zoom Inzoom in Zoom Outzoom out
 21 / 40 page
background image
DS782F1
21
CS4349
4.4
De-Emphasis
The device includes on-chip digital de-emphasis. Figure 16 shows the de-emphasis curve for Fs equal to
44.1 kHz. The frequency response of the de-emphasis curve scales proportionally with changes in sample
rate, Fs.
Note:
De-emphasis is only available in Single-Speed Mode.
4.5
Mute Control
The mute control pins (AMUTEC and BMUTEC) go active during power-up initialization, reset, muting (see
Section 8.4.3), and loss of LRCK. These pins are intended to be used as control for external mute circuits
to prevent the clicks and pops that can occur in any single-ended single-supply system.
Use of the mute control function is not mandatory but recommended for designs requiring the absolute min-
imum in extraneous clicks and pops. Also, use of the Mute Control function can enable the system designer
to achieve idle-channel noise and signal-to-noise ratios which are only limited by the external mute circuit.
4.6
Recommended Power-Up Sequence
4.6.1
Stand-Alone Mode
1. Hold RST low until the power supplies and configuration pins are stable, and the serial and left/right
clocks are fixed to the appropriate frequencies, as discussed in Section 4.2. In this state, the control
port registers are reset to their default settings, VQ will remain low, and VBIAS will be connected to
VA.
2. Bring RST high. The device will remain in a low power state with VQ low for approximately 512 LRCK
cycles in Single-Speed Mode (1024 LRCK cycles in Double-Speed Mode, and 2048 LRCK cycles in
Quad-Speed Mode).
3. The device will then initiate the power up sequence which lasts approximately 50 µs when the
Popguard is disabled. If the Popguard is enabled, see Section 4.7 for a complete description of
power-up timing.
Gain
dB
-10dB
0dB
Frequency
T2 = 15 µs
T1=50 µs
F1
F2
3.183 kHz
10.61 kHz
Figure 16. De-Emphasis Curve



Html Pages

1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 37 38 39 40


数据表 下载

Go To PDF Page


链接网址



ALLDATASHEET是否为您带来帮助?  [ DONATE ] 

关于 Alldatasheet   |   广告服务   |   联系我们   |   隐私政策   |   数据表链接    |   链接交换   |   制造商名单
All Rights Reserved©Alldatasheet.com


Mirror Sites
English : Alldatasheet.com  |   English : Alldatasheet.net  |   Chinese : Alldatasheetcn.com  |   German : Alldatasheetde.com  |   Japanese : Alldatasheet.jp
Russian : Alldatasheetru.com  |   Korean : Alldatasheet.co.kr  |   Spanish : Alldatasheet.es  |   French : Alldatasheet.fr  |   Italian : Alldatasheetit.com
Portuguese : Alldatasheetpt.com  |   Polish : Alldatasheet.pl  |   Vietnamese : Alldatasheet.vn
Indian : Alldatasheet.in  |   Mexican : Alldatasheet.com.mx  |   British : Alldatasheet.co.uk  |   New Zealand : Alldatasheet.co.nz
Family Site : ic2ic.com  |   icmetro.com