Data Sheet

ADL8111

PIN CONFIGURATION AND FUNCTION DESCRIPTIONS

analog.com

Rev. A | 6 of 24

Figure 5. Pin Configuration—Top View Not to Scale

Table 7. Pin Function Descriptions

Pin No.

Mnemonic

Description

1

VDD_PA

Drain Bias Voltage. See Table 2.

2

VBIAS

Current Mirror Bias Resistor Pin. Use this pin to set the current to the internal resistor by the external resistor. See

Figure 9 for the interface schematic.

3, 5, 8, 10 to 12, 14, 17, 19 to 22, 24

to 26, 28

GND

RF and DC Ground. See Figure 6 for the interface schematic.

4

RFIN

RF Input. These pins are dc-coupled and matched to 50 Ω. A dc blocking capacitor is required if the RF line potential

is not equal to 0 V dc.

6, 7

VA, VB

Control Input. See Table 2, Table 4, and Table 5. See Figure 8 and Figure 7 for the interface schematics.

9, 13

OUT_B, IN_B

These pins are dc-coupled and matched to 50 Ω. A dc blocking capacitor is required if the RF line potential is not

equal to 0 V dc.

15

VSS_SW

Negative Bias Voltage. See Table 2.

16

VDD_SW

Positive Bias Voltage. See Table 2.

18

RFOUT

RF Output. This pin is dc-coupled and matched to 50 Ω. A dc blocking capacitor is required if the RF line potential is

not equal to 0 V dc.

23, 27

IN_A, OUT_A

These pins are dc-coupled and matched to 50 Ω. A dc blocking capacitor is required if the RF line potential is not

equal to 0 V dc.

EPAD

Exposed Pad. The exposed pad must be connected to RF and dc ground.

INTERFACE SCHEMATICS

Figure 6. GND Interface Schematic

Figure 7. VB Interface Schematic

Figure 8. VA Interface Schematic

Figure 9. VBIAS Interface Schematic

Figure 10. RFIN and RFOUT Interface Schematic