Data Sheet

ADRF5545A

Rev. B | Page 5 of 20

ABSOLUTE MAXIMUM RATINGS

Table 3.

Parameter

Rating

Positive Supply Voltage

VDD1-CHA, VDD1-CHB, VDD2-CHA,

VDD2-CHB

7 V

SWVDD-CHAB

5.4 V

Digital Control Input Voltage

SWCTRL-CHAB

−0.3 V to VDD1+ 0.3 V

BP-CHA, BP-CHB, PD-CHAB

−0.3 V to VDD1+ 0.3 V

RF Input Power

Transmit Input Power (LTE Peak)

53 dBm

Receive Input Power (LTE Peak)

25 dBm

Temperature

Storage

−65°C to +150°C

Reflow

260°C

Electrostatic Discharge (ESD)

Sensitivity

Human Body Model (HBM)

500 V, Class 1B

Charge Device Model (CDM)

1.25 kV

1

VDD is the voltage of the SWVDD-CHAB, VDD1-CHA, VDD1-CHB, VDD2-CHA, and

VDD2-CHB pins.

Stresses at or above those listed under Absolute Maximum

Ratings may cause permanent damage to the product. This is a

stress rating only; functional operation of the product at these

or any other conditions above those indicated in the

operational section of this specification is not implied.

Operation beyond the maximum operating conditions for

extended periods may affect product reliability.

THERMAL RESISTANCE

Thermal performance is directly linked to printed circuit board

(PCB) design and operation environment. Careful attention to

PCB thermal design is required.

θJC is the junction to case bottom (channel to package bottom)

thermal resistance.

Table 4. Thermal Resistance

Package Type

θJC

Unit

CP-40-15

High Gain and Low Gain Mode

30

°C/W

Power-Down Mode

8.7

°C/W

ESD CAUTION