CS42528 datasheet(32/91 Pages) CIRRUS

32 / 91 page

DS586F1

CS42528

4.6.3

ADCIN1/ADCIN2 Serial Data Format

The two serial data lines which interface to the optional external ADCs, ADCIN1 and ADCIN2, support

only left-justified, 24-bit samples at 64Fs or 128Fs. This interface is not affected by any of the serial port

configuration register bit settings. These serial data lines are used when supporting One-Line Mode of

operation with external ADCs attached. If these signals are not being used, they should be tied together

and wired to GND via a pull-down resistor.

For proper operation, the CS42528 must be configured to select which SCLK/LRCK is being used to clock

the external ADCs. The EXT ADC SCLK bit in register “Misc Control (address 05h)” on page 51 must be

set accordingly. Set this bit to ‘1’ if the external ADCs are wired using the CODEC_SP clocks. If the ADCs

are wired to use the SAI_SP clocks, set this bit to ‘0’.

CX_LRCK

SAI_LRCK

CX_SCLK

SAI_SCLK

Left Channel

Right Channel

ADCIN1/2

+3 +2 +1

+5 +4

-1 -2 -3 -4 -5

+3 +2 +1

+5 +4

-1 -2 -3 -4

MSB

LSB

MSB

LSB

Figure 15. ADCIN1/ADCIN2 Serial Audio Format

Left-Justified Mode, Data Valid on Rising Edge of SCLK

Bits/Sample

SCLK Rate(s)

Notes

64, 128 Fs

Single-Speed Mode, Fs= 32, 44.1, 48 kHz

64 Fs

Double-Speed Mode, Fs= 64, 88.2, 96 kHz

not supported

Quad-Speed Mode, Fs= 176.4, 192 kHz

CS42528 数据表(PDF) 32 Page - Cirrus Logic

CS42528 数据表(HTML) 32 Page - Cirrus Logic

Html Pages

1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 48 49 50 51 52 53 54 55 56 57 58 59 60 61 62 63 64 65 66 67 68 69 70 71 72 73 74 75 76 77 78 79 80 81 82 83 84 85 86 87 88 89 90 91

数据表下载