CS42528 datasheet(36/91 Pages) CIRRUS

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DS586F1

CS42528

4.6.4.4

OLM Config #4

This configuration will support up to 8 channels of DAC data 6 channels of ADC data and no channels of

S/PDIF received data. OLM Config #4 will handle up to 20-bit ADC samples at an Fs of 48 kHz and 24-bit

DAC samples at an Fs of 48 kHz. Since the ADC’s data stream is configured to use the SAI_SDOUT output

and the internal and external ADCs are clocked from the SAI_SP, the sample rate for the CODEC Serial

Port can be different from the sample rate of the Serial Audio Interface serial port.

Description

Functional Mode Register (addr = 03h)

Set CODEC_FMx = 00,01,10

CX_LRCK can run at SSM, DSM, or QSM independent of SAI_LRCK

Set SAI_FMx = 00,01,10

SAI_LRCK can run at SSM, DSM, or QSM independent of CX_LRCK

Set ADC_SP SELx = 10

Configure ADC data to use SAI_SDOUT and SAI_SP Clocks. S/PDIF data

is not supported in this configuration

Interface Format Register (addr = 04h)

Set DIFx bits to proper serial format

Select the digital interface format when not in one line mode

Set ADC_OLx bits = 00,01

Select ADC operating mode, see table below for valid combinations

Set DAC_OLx bits = 00,01,10

Select DAC operating mode, see table below for valid combinations

Misc. Control Register (addr = 05h)

Set CODEC_SP M/S = 1

Set DAC Serial Port to master mode.

Set SAI_SP M/S = 0 or 1

Set ADC Serial Port to master mode or slave mode.

Set EXT ADC SCLK = 0

Identify external ADC clock source as SAI Serial Port.

CX_SDOUT= not used

SAI_SDOUT=ADC Data

DAC Mode

Not One Line Mode

One Line Mode #1

One Line Mode #2

ADC Mode

Not One-

Line Mode

CX_SCLK=64 Fs

CX_LRCK=SSM/DSM/QSM

SAI_SCLK=64 Fs

SAI_LRCK=SSM/DSM/QSM

CX_SCLK=128 Fs

CX_LRCK=SSM/DSM

SAI_SCLK=64 Fs

SAI_LRCK=SSM/DSM/QSM

CX_SCLK=256 Fs

CX_LRCK=SSM

SAI_SCLK=64 Fs

SAI_LRCK=SSM/DSM/QSM

One-Line

Mode #1

CX_SCLK=64 Fs

CX_LRCK=SSM/DSM/QSM

SAI_SCLK=128 Fs

SAI_LRCK=SSM

CX_SCLK=128 Fs

CX_LRCK=SSM/DSM

SAI_SCLK=128 Fs

SAI_LRCK=SSM

CX_SCLK=256 Fs

CX_LRCK=SSM

SAI_SCLK=128 Fs

SAI_LRCK=SSM

One-Line

Mode #2

not valid

SCLK_PORT1

LRCK_PORT1

SDIN_PORT1

SCLK_PORT2

LRCK_PORT2

SDIN_PORT2

SCLK_PORT3

LRCK_PORT3

SDOUT1_PORT3

SDOUT2_PORT3

SDOUT3_PORT3

SDOUT4_PORT3

RMCK

ADCIN1

ADCIN2

MCLK

SDOUT1

SDOUT2

LRCK

SCLK

64Fs,128Fs,256Fs

ADC Data

64Fs,128Fs

DIGITAL AUDIO

PROCESSOR

CS5361

SAI_SCLK

SAI_LRCK

SAI_SDOUT

CX_SCLK

CX_LRCK

CX_SDOUT

CX_SDIN1

CX_SDIN2

CX_SDIN3

CX_SDIN4

MCLK

Figure 19. OLM Configuration #4

CS42528

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