PCA9502_3

© NXP B.V. 2006. All rights reserved.

Product data sheet

Rev. 03 — 13 October 2006

4 of 25

NXP Semiconductors

PCA9502

[1]

See Section 7.1 “Hardware reset, Power-On Reset (POR) and software reset”

7.

Functional description

I2C/SPI pin), and provides the host with eight programmable GPIO pins.

7.1 Hardware reset, Power-On Reset (POR) and software reset

These three reset methods are identical and will reset the internal registers as indicated in

Table 3.

Table 3 summarizes the state of registers after reset.

Table 4 summarizes the state of hardware pins after reset.

IRQ

12

O

Interrupt (open-drain, active LOW). Interrupt is enabled when

interrupt sources are enabled in the I/O Interrupt Enable register

(IOIntEna). The interrupt condition is the change of state of the

input pins. An external resistor (1 k

Ω for 3.3 V, 1.5 kΩ for 2.5 V)

GPIO0

13

I/O

programmable I/O pin

GPIO1

14

I/O

programmable I/O pin

GPIO2

15

I/O

programmable I/O pin

GPIO3

16

I/O

programmable I/O pin

GPIO4

18

I/O

programmable I/O pin

GPIO5

19

I/O

programmable I/O pin

GPIO6

20

I/O

programmable I/O pin

GPIO7

21

I/O

programmable I/O pin

10, 17,

23

-

ground

center

pad

-

The center pad on the back side of the HVQFN24 package is

metallic and should be connected to ground on the printed-circuit

board.

Table 2.

Symbol

Pin

Type

Description

Table 3.

Registers after reset

Register

Reset state

I/O direction

all bits cleared

I/O interrupt enable

all bits cleared

I/O control

all bits cleared

Table 4.

Signals after reset

Signal

Reset state

I/Os

inputs

IRQ

HIGH by external pull-up