PCA9502_3

© NXP B.V. 2006. All rights reserved.

Product data sheet

Rev. 03 — 13 October 2006

3 of 25

NXP Semiconductors

PCA9502

6.

Pinning information

6.1 Pinning

6.2 Pin description

b. SPI interface

Fig 3.

Pin configuration for HVQFN24

GPIO4

GPIO2

GPIO1

GPIO0

A1

A0

RESET

GPIO3

002aab839

Transparent top view

terminal 1

index area

6

13

5

14

4

15

3

16

2

17

1

18

PCA9502BS

GPIO4

GPIO2

GPIO1

GPIO0

SI

CS

RESET

GPIO3

002aab840

Transparent top view

terminal 1

index area

6

13

5

14

4

15

3

16

2

17

1

18

PCA9502BS

Table 2.

Pin description

Symbol

Pin

Type

Description

RESET

1

I

device hardware reset (active LOW)[1]

2, 3, 11,

22, 24

-

power supply

I2C/SPI

4

I

pin is at logic HIGH. SPI interface is selected if this pin is at logic

LOW.

CS/A0

5

I

configuration is selected by I2C/SPI pin, this pin is the SPI chip

is selected by I2C/SPI pin, this pin along with A1 pin allows user

to change the device’s base address.

SI/A1

6

I

configuration is selected by I2C/SPI pin, this is the SPI data input

along with A0 pin allows user to change the device’s base

address. To select the device address, please refer to Table 11.

SO

7

O

SPI data output pin. If SPI configuration is selected by I2C/SPI

selected by I2C/SPI pin, this pin function is undefined and must

be left as n.c. (not connected).

SCL/SCLK

8

I

SDA

9

I/O

selected by I2C/SPI pin. If SPI configuration is selected then this